A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA

Henry Block, Tsutomu Maruyama. A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA. In 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013. pages 318-321, IEEE, 2013. [doi]

@inproceedings{BlockM13,
  title = {A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA},
  author = {Henry Block and Tsutomu Maruyama},
  year = {2013},
  doi = {10.1109/FPT.2013.6718376},
  url = {http://dx.doi.org/10.1109/FPT.2013.6718376},
  researchr = {https://researchr.org/publication/BlockM13},
  cites = {0},
  citedby = {0},
  pages = {318-321},
  booktitle = {2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013},
  publisher = {IEEE},
}