Abstract is missing.
- Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural NetworksMartin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk. 3-13 [doi]
- Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware DesignGiovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi. 14-29 [doi]
- Optimising Operator Sets for Analytical Database Processing on FPGAsAnna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck. 30-44 [doi]
- Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator SystemsAlberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre. 45-60 [doi]
- Chisel Usecase: Designing General Matrix Multiply for FPGABruno Ferres, Olivier Muller, Frédéric Rousseau. 61-72 [doi]
- Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural NetworksHabib ul Hasan Khan, Ariel Podlubne, Gökhan Akgün, Diana Göhringer. 73-83 [doi]
- Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAsLudovica Bozzoli, Luca Sterpone. 84-96 [doi]
- SysIDLib: A High-Level Synthesis FPGA Library for Online System IdentificationGökhan Akgün, Habib ul Hasan Khan, Marawan Hebaish, Mahmoud Ahmed Elshimy, Mohamed A. Abd El ghany, Diana Göhringer. 97-107 [doi]
- Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing DevicesZakarya Guettatfi, Paul Kaufmann, Marco Platzner. 108-117 [doi]
- Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAsPascal Bacchus, Robert J. Stewart, Ekaterina Komendantskaya. 121-135 [doi]
- Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCsLeonardo Suriano, David Lima, Eduardo de la Torre. 136-150 [doi]
- Cross-layer CNN Approximations for Hardware ImplementationKarim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, Smaïl Niar. 151-165 [doi]
- Technique for Vendor and Device Agnostic Hardware Area-Time EstimationDeshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan, Thilina Perera. 166-177 [doi]
- Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAsGökhan Akgün, Lester Kalms, Diana Göhringer. 178-192 [doi]
- RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and PerformanceMuhammad Ali, Pedram Amini Rad, Diana Göhringer. 193-207 [doi]
- A Modular Software Library for Effective High Level Synthesis of Convolutional Neural NetworksHector Gerardo Muñoz Hernandez, Safdar Mahmood, Marcelo Brandalero, Michael Hübner. 211-220 [doi]
- HLS-Based Acceleration Framework for Deep Convolutional Neural NetworksAshish Misra, Volodymyr Kindratenko. 221-231 [doi]
- FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design MethodChangdao Du, Iman Firmansyah, Yoshiki Yamaguchi. 232-246 [doi]
- High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware CodesignDuc Tri Nguyen, Viet B. Dang, Kris Gaj. 247-257 [doi]
- Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra KernelsFederico Favaro, Ernesto Dufrechou, Pablo Ezzatti, Juan P. Oliver. 258-268 [doi]
- A CGRA Definition Framework for Dataflow ApplicationsGeorge Charitopoulos, Dionisios N. Pnevmatikatos. 271-287 [doi]
- Implementing CNNs Using a Linear Array of Full Mesh CGRAsValter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa. 288-297 [doi]
- A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence AlignmentRiadh Ben Abdelhamid, Yoshiki Yamaguchi. 298-313 [doi]
- Comparison of Direct and Indirect Networks for High-Performance FPGA ClustersAntoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa. 314-329 [doi]
- A Parameterisable FPGA-Tailored Architecture for YOLOv3-TinyZhewen Yu, Christos-Savvas Bouganis. 330-344 [doi]
- Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAsTaiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki. 345-357 [doi]
- StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip ArchitecturesArshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani, Dmitriy Fedorov. 361-375 [doi]
- Implementation of FM-Index Based Pattern Search on a Multi-FPGA SystemM. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano. 376-391 [doi]
- Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection AlgorithmRui Policarpo Duarte, Helena Cruz, Horácio C. Neto. 392-401 [doi]