Abstract is missing.
- Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices ApplicationsLin Cheng 0001, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu. 1-2 [doi]
- A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOSSujin Park, Geon-Hwi Lee, Seungmin Oh, SeongHwan Cho. 3-4 [doi]
- A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NRZheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang 0008, Dongwon You, Ashbir Aviat Fadila, Joshua Alvin, Bangan Liu, Zheng Sun, Hongye Huang, Atsushi Shirane, Kenichi Okada. 5-6 [doi]
- A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking SystemChing-Hwa Cheng. 7-8 [doi]
- An Inductively Coupled Wireless Bus for Chiplet-Based SystemsJunichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai. 9-10 [doi]
- FPGA-based Heterogeneous Solver for Three-Dimensional RoutingKento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa. 11-12 [doi]
- PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural NetworkZhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen. 13-18 [doi]
- FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter TuningZhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza. 19-25 [doi]
- High-Definition Routing Congestion Prediction for Large-Scale FPGAsMohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan. 26-31 [doi]
- Integrated Airgap Insertion and Layer Reassignment for Circuit Timing optimizationYounggwang Jung, Daijoon Hyun, Youngsoo Shin. 32-37 [doi]
- An Adaptive Electromigration Assessment Algorithm for Full-chip Power/Ground NetworksShaobin Ma, Xiaoyi Wang, Sheldon X.-D. Tan, Liang Chen, Jian He. 38-43 [doi]
- Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN TechniquesVidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu. 44-49 [doi]
- Analyzing The Security of The Cache Side Channel Defences With Attack GraphsLimin Wang, Ziyuan Zhu, Zhanpeng Wang, Dan Meng. 50-55 [doi]
- iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPUWenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das. 56-61 [doi]
- Design for EM Side-Channel Security through Quantitative Assessment of RTL ImplementationsJiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin. 62-67 [doi]
- Impact of Self-Heating on Performance, Power and Reliability in FinFET TechnologyVictor M. van Santen, Paul R. Genssler, Om Prakash, Simon Thomann, Jörg Henkel, Hussam Amrouch. 68-73 [doi]
- Reliable Power Grid Network Design Framework Considering EM Immortalities for Multi-Segment WiresHan Zhou, Shuyuan Yu, Zeyu Sun, Sheldon X.-D. Tan. 74-79 [doi]
- Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System SimulationUzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 80-84 [doi]
- Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial IntelligenceLei Yang, Weiwen Jiang, Weichen Liu, Edwin H.-M. Sha, Yiyu Shi, Jingtong Hu. 85-90 [doi]
- Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-DecompositionDae-Hee Kim, Rakesh Nagi, Deming Chen. 91-96 [doi]
- Reutilization of Trace Buffers for Performance Enhancement of NoC based MPSoCsSidhartha Sankar Rout, Badri M, Sujay Deb. 97-102 [doi]
- Formal Semantics of Predictable Pipelines: a Comparative StudyMathieu Jan, Mihail Asavoae, Martin Schoeberl, Edward A. Lee. 103-108 [doi]
- Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-ChipsMengchu Li, Tsun-Ming Tseng, Mahdi Tala, Ulf Schlichtmann. 109-114 [doi]
- Concurrency in DD-based Quantum Circuit SimulationStefan Hillmich, Alwin Zulehner, Robert Wille. 115-120 [doi]
- Approximation of Quantum States Using Decision DiagramsAlwin Zulehner, Stefan Hillmich, Igor L. Markov, Robert Wille. 121-126 [doi]
- Improved DD-based Equivalence Checking of Quantum CircuitsLukas Burgholzer, Robert Wille. 127-132 [doi]
- Equivalent Capacitance Guided Dummy Fill Insertion for Timing and ManufacturabilitySheng-Jung Yu, Chen-Chien Kao, Chia-Han Huang, Iris Hui-Ru Jiang. 133-138 [doi]
- Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process NodesJeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi. 139-144 [doi]
- Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied AugmentationChaofei Yang, Hai Li, Yiran Chen, Jiang Hu. 145-150 [doi]
- Exploring Graphical Models with Bayesian Learning and MCMC for Failure DiagnosisHongfei Wang, Wenjie Cai, Jianwen Li, Kun He 0001. 151-156 [doi]
- Mitigating Adversarial Attacks for Deep Neural Networks by Input Deformation and AugmentationPengfei Qiu, Qian Wang, Dongsheng Wang, Yongqiang Lyu, Zhaojun Lu, Gang Qu. 157-162 [doi]
- When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and RemediesZheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo. 163-168 [doi]
- Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output PartitionsElbruz Ozen, Alex Orailoglu. 169-174 [doi]
- PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAMFan Chen, Linghao Song, Hai Helen Li, Yiran Chen. 175-180 [doi]
- RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory ArchitecturesShikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza. 181-186 [doi]
- Defects Mitigation in Resistive Crossbars for Analog Vector Matrix MultiplicationFan Zhang, Miao Hu. 187-192 [doi]
- 3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph SimilarityMingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan. 193-198 [doi]
- Establishing Reachset Conformance for the Formal Analysis of Analog CircuitsNiklas Kochdumper, Ahmad Tarraf, Malgorzata Rechmal, Markus Olbrich, Lars Hedrich, Matthias Althoff. 199-204 [doi]
- Contention Minimized Bypassing in SMART NoCPeng Chen, Weichen Liu, Mengquan Li, Lei Yang, Nan Guan. 205-210 [doi]
- FTT-NAS: Discovering Fault-Tolerant Neural ArchitectureWenshuo Li, Xuefei Ning, Guangjun Ge, Xiaoming Chen, Yu Wang 0002, Huazhong Yang. 211-216 [doi]
- The Notion of Cross Coverage in AMS Design VerificationSayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian. 217-222 [doi]
- Automated Test Generation for Activation of Assertions in RTL ModelsYangdi Lyu, Prabhat Mishra. 223-228 [doi]
- Machine Learning Based Online Full-Chip Heatmap EstimationSheriff Sadiqbatcha, Yue Zhao, Jinwei Zhang, Hussam Amrouch, Jörg Henkel, Sheldon X.-D. Tan. 229-234 [doi]
- A Reconfigurable Approximate Multiplier for Quantized CNN ApplicationsChuliang Guo, Li Zhang, Xian Zhou, Weikang Qian, Cheng Zhuo. 235-240 [doi]
- EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing UnitNoel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang. 241-246 [doi]
- Towards Efficient Kyber on FPGAs: A Processor for Vector of PolynomialsZhaohui Chen, Yuan Ma, Tianyu Chen, Jingqiang Lin, Jiwu Jing. 247-252 [doi]
- m) based on Bivariate Polynomial Basis RepresentationChiou-Yng Lee, Jiafeng Xie. 253-258 [doi]
- Security Threats and Countermeasures for Approximate Arithmetic ComputingPruthvy Yellu, Mohammad Mezanur Rahman Monjur, Timothy Kammerer, Dongpeng Xu, Qiaoyan Yu. 259-264 [doi]
- Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel ComputingHemanta Kumar Mondal, Navonil Chatterjee, Rodrigo Cataldo, Jean-Philippe Diguet. 265-270 [doi]
- A Generic FPGA Accelerator for Minimum Storage Regenerating CodesMian Qin, Joo Hwan Lee, Rekha Pitchumani, Yang-Seok Ki, A. L. Narasimha Reddy, Paul V. Gratz. 271-276 [doi]
- Parallel-Log-Single-Compaction-Tree: Flash-Friendly Two-Level Key-Value Management in KVSSDsYen-Ting Chen, Ming-Chang Yang, Yuan-Hao Chang, Wei Kuan Shih. 277-282 [doi]
- Towards Design Methodology of Efficient Fast Algorithms for Accelerating Generative Adversarial Networks on FPGAsJung-Woo Chang, Saehyun Ahn, Keon-Woo Kang, Suk-Ju Kang. 283-288 [doi]
- Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks AcceleratorBaoting Li, Longjun Liu, Yanming Jin, Peng Gao, Hongbin Sun 0001, Nanning Zheng. 289-294 [doi]
- CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network ArchitecturesMaedeh Hemmat, Tejas Shah, Yuhua Chen, Joshua San Miguel. 295-300 [doi]
- Tiny but Accurate: A Pruned, Quantized and Optimized Memristor Crossbar Framework for Ultra Efficient DNN ImplementationXiaolong Ma, Geng Yuan, Sheng Lin, Caiwen Ding, Fuxun Yu, Tao Liu, Wujie Wen, Xiang Chen, Yanzhi Wang. 301-306 [doi]
- Towards Read-Intensive Key-Value Stores with Tidal Structure Based on LSM-TreeYi Wang, Shangyu Wu, Rui Mao. 307-312 [doi]
- A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural NetworksLi Yang, Shaahin Angizi, Deliang Fan. 313-318 [doi]
- Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System PerformanceReika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi. 319-324 [doi]
- An Energy-Efficient Quantized and Regularized Training Framework For Processing-In-Memory AcceleratorsHanbo Sun, Zhenhua Zhu, Yi Cai, Xiaoming Chen, Yu Wang, Huazhong Yang. 325-330 [doi]
- Unified Redistribution Layer Routing for 2.5D IC PackagesChun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang. 331-337 [doi]
- AIR: A Fast but Lazy Timing-Driven FPGA RouterKevin E. Murray, Sheng Zhong, Vaughn Betz. 338-344 [doi]
- SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nmDongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng. 345-350 [doi]
- Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD ToolsM. D. Arafat Kabir, Yarui Peng. 351-356 [doi]
- Event Delivery using Prediction for Faster Parallel SystemC SimulationZhongqi Cheng, Emad Arasteh, Rainer Dömer. 357-362 [doi]
- Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level ModelsGabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy. 363-368 [doi]
- JIT-Based Context-Sensitive Timing Simulation for Efficient Platform ExplorationAlessandro Cornaglia, Md. Shakib Hasan, Alexander Viehl, Oliver Bringmann 0001, Wolfgang Rosenstiel. 369-374 [doi]
- Towards Automatic Hardware Synthesis from Formal Specification to ImplementationFritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler. 375-380 [doi]
- Emerging Non-Volatile Memories for Computation-in-MemoryBin Gao. 381-384 [doi]
- The Power of Computation-in-Memory Based on Memristive DevicesJintao Yu, Muath Abu Lebdeh, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui. 385-392 [doi]
- Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive MemoriesChristopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 393-400 [doi]
- Ferroelectrics: From Memory to ComputingKai Ni 0004, Sourav Dutta, Suman Datta. 401-406 [doi]
- Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET MemoryJuejian Wu, Yixin Xu, Bowen Xue, Yu Wang, Yongpan Liu, Huazhong Yang, Xueqing Li. 407-413 [doi]
- Emerging memories as enablers for in-memory layout transformation acceleration and virtualizationMinli Julie Liao, Jack Sampson. 414-421 [doi]
- Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network TrainingYandong Luo, Shimeng Yu. 422-427 [doi]
- Capacitance Extraction and Power Grid Analysis Using Statistical and AI MethodsWenjian Yu, Ming Yang, Yao Feng, Ganqu Cui, Ben Gu. 428-433 [doi]
- VLSI Mask Optimization: From Shallow To Deep LearningHaoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu 0001. 434-439 [doi]
- Bayesian Methods for the Yield Optimization of Analog and SRAM CircuitsShuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng 0001. 440-445 [doi]
- Programmable Neuromorphic Circuit based on Printed Electrolyte-Gated TransistorsDennis D. Weller, Michael Hefenbrock, Mehdi Baradaran Tahoori, Jasmin Aghassi-Hagmann, Michael Beigl. 446-451 [doi]
- HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision SensorShasha Guo, Ziyang Kang, Lei Wang 0011, Shiming Li, Weixia Xu. 452-457 [doi]
- A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network ImplementationYuki Kume, Song Bian, Takashi Sato. 458-463 [doi]
- MindReading: An Ultra-Low-Power Photonic Accelerator for EEG-based Human Intention RecognitionQian Lou, Wenyang Liu, Weichen Liu, Feng Guo, Lei Jiang 0001. 464-469 [doi]
- LanCe: A Comprehensive and Lightweight CNN Defense Methodology against Physical Adversarial Attacks on Embedded Multimedia ApplicationsZirui Xu, Fuxun Yu, Xiang Chen. 470-475 [doi]
- Towards Area-Efficient Optical Neural Networks: An FFT-based ArchitectureJiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan. 476-481 [doi]
- Automated Trigger Activation by Repeated Maximal Clique SamplingYangdi Lyu, Prabhat Mishra. 482-487 [doi]
- *Kuei-Huan Chang, Po-Hao Huang, Honggang Yu, Yier Jin, Ting-Chi Wang. 488-493 [doi]
- Database and Benchmark for Early-stage Malicious Activity Detection in 3D PrintingXiaolong Ma, Zhe Li, Hongjia Li, Qiyuan An, Qinru Qiu, Wenyao Xu, Yanzhi Wang. 494-499 [doi]
- EA-HRT: An Energy-Aware scheduler for Heterogeneous Real-Time systemsSanjay Moulik, Rishabh Chaudhary, Zinea Das, Arnab Sarkar. 500-505 [doi]
- Insights and Optimizations on IR-drop Induced Sneak-Path for RRAM Crossbar-based ConvolutionsYujie Zhu, Xue Zhao, Keni Qiu. 506-511 [doi]
- Boosting the Profitability of NVRAM-based Storage Devices via the Concept of Dual-Chunking Data DeduplicationShuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang, Hsin-Wen Wei, Wei Kuan Shih. 512-517 [doi]
- Black Box Search Space Profiling for Accelerator-Aware Neural Architecture SearchShulin Zeng, Hanbo Sun, Yu Xing, Xuefei Ning, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang. 518-523 [doi]
- Search-free Accelerator for Sparse Convolutional Neural NetworksBosheng Liu, Xiaoming Chen, Yinhe Han, Ying Wang, Jiajun Li, Haobo Xu, Xiaowei Li 0001. 524-529 [doi]
- NESTA: Hamming Weight Compression-Based Neural Proc. EngineAli MirzaeianAli Mirzaeian, Houman Homayoun, Avesta Sasan. 530-537 [doi]
- Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using MemristorsBaogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz. 538-543 [doi]
- Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA BiochipsZhanwei Zhong, Tung-Che Liang, Krishnendu Chakrabarty. 544-549 [doi]
- Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol ExecutionSatoru Maruyama, Debraj Kundu, Shigeru Yamashita, Sudip Roy 0001. 550-555 [doi]
- An FPGA based Network Interface Card with Query Filter for Storage Nodes of Big Data SystemsYing Li, Jinyu Zhan, Wei Jiang, Junting Wu, Jianping Zhu. 556-561 [doi]
- Nonvolatile and Energy-Efficient FeFET-Based Multiplier for Energy-Harvesting DevicesMengyuan Li, Xunzhao Yin, Xiaobo Sharon Hu, Cheng Zhuo. 562-567 [doi]
- Modulo Scheduling with Rational Initiation Intervals in Custom Hardware DesignPatrick Sittel, John Wickerson, Martin Kumm, Peter Zipf. 568-573 [doi]
- HL-Pow: A Learning-Based Power Modeling Framework for High-Level SynthesisZhe Lin 0007, Jieru Zhao, Sharad Sinha, Wei Zhang. 574-580 [doi]
- DRiLLS: Deep Reinforcement Learning for Logic SynthesisAbdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda. 581-586 [doi]
- Lightening Asynchronous Pipeline Controller Through Resynthesis and OptimizationJeongwoo Heo, Taewhan Kim. 587-592 [doi]
- WEID: Worst-case Error Improvement in Approximate DividersHassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran. 593-598 [doi]
- Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary ModulesYi Guo, Heming Sun, Shinji Kimura. 599-604 [doi]
- LeAp: Leading-one Detection-based Softcore Approximate Multipliers with Tunable AccuracyZahra Ebrahimi, Salim Ullah, Akash Kumar 0001. 605-610 [doi]
- Scaled Population Arithmetic for Efficient Stochastic ComputingHe Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu. 611-616 [doi]
- Soft Error and Its Countermeasures in Terrestrial EnvironmentMasanori Hashimoto, Wang Liao. 617-622 [doi]
- Timing Resilience for Efficient and Secure CircuitsGrace Li Zhang, Michaela Brunner, Bing Li 0005, Georg Sigl, Ulf Schlichtmann. 623-628 [doi]
- Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core SystemsJürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann. 629-636 [doi]
- NCFET to Rescue Technology Scaling: Opportunities and ChallengesHussam Amrouch, Victor M. van Santen, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel. 637-644 [doi]
- Parallelism in Deep Learning AcceleratorsLinghao Song, Fan Chen, Yiran Chen, Hai Helen Li. 645-650 [doi]
- Software-Based Memory Analysis Environments for In-Memory Wear-LevelingChristian Hakert, Kuan-Hsun Chen, Mikail Yayla, Georg von der Brüggen, Sebastian Blömeke, Jian-Jia Chen. 651-658 [doi]
- Theory of Ising Machines and a Common Software Platform for Ising MachinesShu Tanaka, Yoshiki Matsuda, Nozomu Togawa. 659-666 [doi]
- Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its ApplicationsSatoshi Matsubara, Motomu Takatsu, Toshiyuki Miyazawa, Takayuki Shibasaki, Yasuhiro Watanabe, Kazuya Takemoto, Hirotaka Tamura. 667-672 [doi]
- CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization ProblemChihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka. 673-678 [doi]