Table of Contents

• A wide conversion ratio, 92.8% efficiency, 3-level buck converter with adaptive on/off-time control and shared charge pump intermediate voltage regulatorKousuke Miyaji, Yuki Karasawa, Takanobu Fukuoka. 1-2 [doi]
• A three-dimensional millimeter-wave frequency-shift based CMOS biosensor using vertically stacked spiral inductors in LC oscillatorsMaya Matsunaga, Taiki Nakanishi, Atsuki Kobayashi, Kiichi Niitsu. 3-4 [doi]
• 2 0.165V 270pW fully-integrated supply-modulated OOK transmitter in 65nm CMOS for glasses-free, self-powered, and fuel-cell-embedded continuous glucose monitoring contact lensKenya Hayashi, Shigeki Arata, Ge Xu, Shunya Murakami, Cong Dang Bui, Takuyoshi Doike, Maya Matsunaga, Atsuki Kobayashi, Kiichi Niitsu. 5-6 [doi]
• 2D optical imaging using photosystem I photosensor platform with 32x32 CMOS biosensor arrayKiichi Niitsu, Taichi Sakabe, Mariko Miyachi, Yoshinori Yamanoi, Hiroshi Nishihara, Tatsuya Tomo, Kazuo Nakazato. 7-8 [doi]
• Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOSAtsuki Kobayashi, Yuya Nishio, Kenya Hayashi, Shigeki Arata, Kiichi Niitsu. 9-10 [doi]
• A low-voltage CMOS electrophoresis IC using electroless gold plating for small-form-factor biomolecule manipulationKiichi Niitsu, Yuuki Yamaji, Atsuki Kobayashi, Kazuo Nakazato. 11-12 [doi]
• A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technologyLiangjian Lyu, Yu Wang 0046, Chixiao Chen, C.-J. Richard Shi. 13-14 [doi]
• Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supplyNobuaki Kobayashi, Tadayoshi Enomoto. 15-16 [doi]
• Design of heterogeneously-integrated memory system with storage class memories and NAND flash memoriesChihiro Matsui, Ken Takeuchi. 17-18 [doi]
• A 65-nm CMOS fully-integrated circulating tumor cell and exosome analyzer using an on-chip vector network analyzer and a transmission-line-based detection windowTaiki Nakanishi, Maya Matsunaga, Shunya Murakami, Atsuki Kobayashi, Kiichi Niitsu. 19-20 [doi]
• Low standby power CMOS delay flip-flop with data retention capabilityNobuaki Kobayashi, Tadayoshi Enomoto. 21-22 [doi]
• Accelerate pattern recognition for cyber security analysisMohammad Tahghighi, Wei Zhang 0012. 23-24 [doi]
• FPGA laboratory system supporting power measurement for low-power digital designMarco Winzker, Andrea Schwandt. 25-26 [doi]
• Towards limiting the impact of timing anomalies in complex real-time processorsPedro Benedicte, Jaume Abella, Carles Hernández, Enrico Mezzetti, Francisco J. Cazorla. 27-32 [doi]
• SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systemsPetra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 33-38 [doi]
• Partitioned and overhead-aware scheduling of mixed-criticality real-time systemsYuanbin Zhou, Soheil Samii, Petru Eles, Zebo Peng. 39-44 [doi]
• Layout recognition attacks on split manufacturingWenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu. 45-50 [doi]
• Execution of provably secure assays on MEDA biochips to thwart attacksTung-Che Liang, Mohammed Shayan, Krishnendu Chakrabarty, Ramesh Karri. 51-57 [doi]
• TAD: time side-channel attack defense of obfuscated source codeAlexander Fell, Thinh Hung Pham, Siew Kei Lam. 58-63 [doi]
• Leakage-aware thermal management for multi-core systems using piecewise linear model based predictive controlXingxing Guo, Hai Wang 0002, Chi Zhang, He Tang, Yuan Yuan. 64-69 [doi]
• Multi-angle bended heat pipe design using x-architecture routing with dynamic thermal weight on mobile devicesHsuan-Hsuan Hsiao, Hong-Wen Chiou, Yu-Min Lee. 70-75 [doi]
• Fully-automated synthesis of power management controllers from UPFDustin Peterson, Oliver Bringmann. 76-81 [doi]
• Integrated flow for reverse engineering of nanoscale technologiesBernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb. 82-89 [doi]
• NETA: when IP fails, secrets leakTravis Meade, Jason Portillo, Shaojie Zhang, Yier Jin. 90-95 [doi]
• Machine learning and structural characteristics for reverse engineeringJohanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann. 96-103 [doi]
• Towards cognitive obfuscation: impeding hardware reverse engineering based on psychological insightsCarina Wiesen, Nils Albartus, Max Hoffmann 0001, Steffen Becker, Sebastian Wallat, Marc Fyrbiak, Nikol Rummel, Christof Paar. 104-111 [doi]
• Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstreamMaik Ender, Pawel Swierczynski, Sebastian Wallat, Matthias Wilhelm, Paul Martin Knopp, Christof Paar. 112-119 [doi]
• GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMsGuohao Dai, Tianhao Huang, Yu Wang 0002, Huazhong Yang, John Wawrzynek. 120-126 [doi]
• ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networksShaahin Angizi, Zhezhi He, Deliang Fan. 127-132 [doi]
• CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimationXizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui. 133-139 [doi]
• CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systemsSheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xiaowei Li. 140-145 [doi]
• AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chipJinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang, Wenyu Sun, Xueqing Li, Huazhong Yang. 146-151 [doi]
• IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closureAshkan Vakil, Houman Homayoun, Avesta Sasan. 152-159 [doi]
• Learning-based prediction of package power delivery network qualityYi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu. 160-166 [doi]
• Tackling signal electromigration with learning-based detection and multistage mitigationWei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan. 167-172 [doi]
• ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM cachesElham Cheshmikhani, Hamed Farbeh, Hossein Asadi. 173-178 [doi]
• Aging-aware chip health prediction adopting an innovative monitoring strategyYun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang. 179-184 [doi]
• Compiling SU(4) quantum circuits to IBM QX architecturesAlwin Zulehner, Robert Wille. 185-190 [doi]
• Quantum circuit compilers using gate commutation rulesToshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross. 191-196 [doi]
• Scalable design for field-coupled nanocomputing circuitsMarcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler. 197-202 [doi]
• BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexingRyosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi. 203-209 [doi]
• Hybrid binary-unary hardware acceleratorS. Rasoul Faraji, Kia Bazargan. 210-215 [doi]
• Fault tolerance in neuromorphic computing systemsMengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty. 216-223 [doi]
• Build reliable and efficient neuromorphic design with memristor technologyBing Li, Bonan Yan, Chenchen Liu, Hai (Helen) Li. 224-229 [doi]
• Reliable in-memory neuromorphic computing using spintronicsChristopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 230-236 [doi]
• A staircase structure for scalable and efficient synthesis of memristor-aided logicAlwin Zulehner, Kamalika Datta, Indranil Sengupta 0001, Robert Wille. 237-242 [doi]
• On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGADaewoo Kim, Sugil Lee, Jongeun Lee. 243-248 [doi]
• HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computingHouxiang Ji, Li Jiang 0002, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang. 249-254 [doi]
• Efficient sparsification of dense circuit matrices in model order reductionCharalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis. 255-260 [doi]
• Spectral approach to verifying non-linear arithmetic circuitsCunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski. 261-267 [doi]
• 2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuitsMohamed Baker Alawieh, Xiyuan Tang, David Z. Pan. 268-273 [doi]
• Energy-efficient, low-latency realization of neural networks through boolean logic minimizationMahdi Nazemi, Ghasem Pasandi, Massoud Pedram. 274-279 [doi]
• Log-quantized stochastic computing for memory and computation efficient DNNsHyeon Uk Sim, Jongeun Lee. 280-285 [doi]
• Cell division: weight bit-width reduction technique for convolutional neural network hardware acceleratorsHanmin Park, Kiyoung Choi. 286-291 [doi]
• LithoROC: lithography hotspot detection with explicit ROC optimizationWei Ye, Yibo Lin, Meng Li 0004, Qiang Liu, David Z. Pan. 292-298 [doi]
• Detecting multi-layer layout hotspots with adaptive squish patternsHaoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu. 299-304 [doi]
• A local optimal method on DSA guiding template assignment with redundant/dummy via insertionXingquan Li, Bei Yu, Jianli Chen, Wenxing Zhu. 305-310 [doi]
• Deep learning-based framework for comprehensive mask optimizationBo-Yi Yu, Yong Zhong, Shao-Yun Fang, Hung-Fei Kuo. 311-316 [doi]
• AxDNN: towards the cross-layer design of approximate DNNsYingHui Fan, Xiaoxi Wu, Jiying Dong, Zhi Qi. 317-322 [doi]
• Simulate-the-hardware: training accurate binarized neural networks for low-precision neural acceleratorsJiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li. 323-328 [doi]
• An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN acceleratorsJingyu Wang, Zhe Yuan, Ruoyang Liu, Huazhong Yang, Yongpan Liu. 329-334 [doi]
• Maximizing power state cross coverage in firmware-based power managementVladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. 335-340 [doi]
• Improving scan chain diagnostic accuracy using multi-stage artificial neural networksMason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng. 341-346 [doi]
• Testing stuck-open faults of priority address encoder in content addressable memoriesTsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun. 347-351 [doi]
• ScanSAT: unlocking obfuscated scan chainsLilas Alrahis, Muhammad Yasin, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu. 352-357 [doi]
• CycSAT-unresolvable cyclic logic encryption using unreachable statesAmin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, Hai Zhou. 358-363 [doi]
• Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliabilityMengquan Li, Weichen Liu, Lei Yang 0018, Peng Chen, Duo Liu, Nan Guan. 364-369 [doi]
• Bidirectional tuning of microring-based silicon photonic transceivers for optimal energy efficiencyYuyang Wang, M. Ashkan Seyedi, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng. 370-375 [doi]
• Redeeming chip-level power efficiency by collaborative management of the computation and communicationNing Lin, Hang Lu, Xin Wei, Xiaowei Li 0001. 376-381 [doi]
• A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designsMoon Gi Seok, Hessam S. Sarjoughian, Daejin Park. 382-387 [doi]
• A sharing-aware L1.5D cache for data reuse in GPGPUsJianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing. 388-393 [doi]
• NeuralHMC: an efficient HMC-based accelerator for deep neural networksChuhan Min, Jiachen Mao, Hai Li, Yiran Chen. 394-399 [doi]
• Boosting chipkill capability under retention-error induced reliability emergencyXianWei Zhang, Rujia Wang, Youtao Zhang, Jun Yang. 400-405 [doi]
• SRAF insertion via supervised dictionary learningHao Geng, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu. 406-411 [doi]
• A fast machine learning-based mask printability predictor for OPC accelerationBentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young. 412-419 [doi]
• Semi-supervised hotspot detection with self-paced multi-task learningYing Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan. 420-425 [doi]
• Exploring emerging CNFET for efficient last level cache designDawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li. 426-431 [doi]
• Mosaic: an automated synthesis flow for boolean logic based on memristor crossbarLei Xie. 432-437 [doi]
• Handling stuck-at-faults in memristor crossbar arrays using matrix transformationsBaogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz. 438-443 [doi]
• CAPTOR: a class adaptive filter pruning framework for convolutional neural networks in mobile applicationsZhuwei Qin, Fuxun Yu, Chenchen Liu, Xiang Chen 0010. 444-449 [doi]
• TNPU: an efficient accelerator architecture for training convolutional neural networksJiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Junchao Yan, Xiaowei Li 0001. 450-455 [doi]
• REIN: a robust training method for enhancing generalization ability of neural networks in autonomous driving systemsFuxun Yu, Chenchen Liu, Xiang Chen 0010. 456-461 [doi]
• Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochipsSohini Saha, Debraj Kundu, Sudip Roy 0001, Sukanta Bhattacharjee, Krishnendu Chakrabarty, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya. 462-467 [doi]
• Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochipsTung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee. 468-473 [doi]
• Robust sample preparation on digital microfluidic biochipsZhanwei Zhong, Robert Wille, Krishnendu Chakrabarty. 474-480 [doi]
• SAADI: a scalable accuracy approximate divider for dynamic energy-quality scalingSetareh Behroozi, Jingjie Li, Jackson Melchert, Younghyun Kim. 481-486 [doi]
• SeFAct: selective feature activation and early classification for CNNsFarhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar. 487-492 [doi]
• FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexityMohsen Imani, Sahand Salamat, Saransh Gupta, Jiani Huang, Tajana Rosing. 493-498 [doi]
• ADMM attack: an enhanced adversarial attack for deep neural networks with undetectable distortionsPu Zhao, Kaidi Xu, Sijia Liu 0001, Yanzhi Wang, Xue Lin. 499-505 [doi]
• A system-level perspective to understand the vulnerability of deep learning systemsTao Liu, Nuo Xu, Qi Liu, Yanzhi Wang, Wujie Wen. 506-511 [doi]
• HAMPER: high-performance adaptive mobile security enhancement against malicious speech and image recognitionZirui Xu, Fuxun Yu, Chenchen Liu, Xiang Chen. 512-517 [doi]
• AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systemsHsin-Pai Cheng, Juncheng Shen, Huanrui Yang, Qing Wu, Hai Li, Yiran Chen. 518-525 [doi]
• SIMULTime: Context-sensitive timing simulation on intermediate code representation for rapid platform explorationsAlessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 526-531 [doi]
• Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadlineAmirhossein Esmaili, Mahdi Nazemi, Massoud Pedram. 532-537 [doi]
• Phone-nomenon: a system-level thermal simulator for handheld devicesHong-Wen Chiou, Yu-Min Lee, Shin-Yu Shiau, Chi-Wen Pan, Tai-Yu Chen. 538-543 [doi]
• Virtual prototyping of heterogeneous automotive applications: matlab, SystemC, or both?Xiao Pan, Carna Zivkovic, Christoph Grimm 0001. 544-549 [doi]
• Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSISun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang. 550-556 [doi]
• MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designsYen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo. 557-562 [doi]
• A shape-driven spreading algorithm using linear programming for global placementShounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan. 563-568 [doi]
• Finding placement-relevant clusters with fast modularity-based clusteringMateus Fogaça, Andrew B. Kahng, Ricardo Reis, Lutong Wang. 569-576 [doi]
• An approximation algorithm to the optimal switch control of reconfigurable battery packsShih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang. 577-584 [doi]
• Autonomous vehicle routing in multiple intersectionsSheng-Hao Lin, Tsung-Yi Ho. 585-590 [doi]
• GRAM: graph processing in a ReRAM-based computational memoryMinxuan Zhou, Mohsen Imani, Saransh Gupta, Yeseong Kim, Tajana Rosing. 591-596 [doi]
• ADEPOS: anomaly detection based power saving for predictive maintenance using edge computingSumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Arindam Basu. 597-602 [doi]
• Efficient sporadic task handling in parallel AUTOSAR applications using runnable migrationMilan Copic, Rainer Leupers, Gerd Ascheid. 603-608 [doi]
• A heuristic for multi objective software application mappings on heterogeneous MPSoCsGereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen. 609-614 [doi]
• ReRAM-based processing-in-memory architecture for blockchain platformsFang Wang, Zhaoyan Shen, Lei Han, Zili Shao. 615-620 [doi]
• Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filterSong Bian, Masayuki Hiromoto, Takashi Sato. 621-626 [doi]
• A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistanceNimesh Shah, Manaar Alam, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Arindam Basu. 627-632 [doi]
• 3M: a PIM-based neural network model protection scheme for deep learning acceleratorWen Li, Ying Wang, Huawei Li, Xiaowei Li. 633-638 [doi]
• Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based acceleratorJilan Lin, Zhenhua Zhu, Yu Wang, Yuan Xie 0001. 639-644 [doi]
• In-memory batch-normalization for resistive memory based binary neural network hardwareHyungJun Kim, Yulhwa Kim, Jae-Joon Kim. 645-650 [doi]
• XOMA: exclusive on-chip memory architecture for energy-efficient deep learning accelerationHyeon Uk Sim, Jason Helge Anderson, Jongeun Lee. 651-656 [doi]
• BeSAT: behavioral SAT-based attack on cyclic logic encryptionYuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, Hai Zhou. 657-662 [doi]
• Structural rewriting in XOR-majority graphsZhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli. 663-668 [doi]
• Design automation for adiabatic circuitsAlwin Zulehner, Michael P. Frank, Robert Wille. 669-674 [doi]
• A figure of merit for assertions in verificationSamuel Hertz, Debjit Pal, Spencer Offenberger, Shobha Vasudevan. 675-680 [doi]
• Suspect2vec: a suspect prediction model for directed RTL debuggingNeil Veira, Zissis Poulos, Andreas G. Veneris. 681-686 [doi]
• Path controllability analysis for high quality designsLi-jie Chen, Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo, Chi-Lai Huang. 687-692 [doi]
• Implementing neural machine translation with bi-directional GRU and attention mechanism on FPGAs using HLSQin Li, Xiaofan Zhang, Jinjun Xiong, Wen-mei Hwu, Deming Chen. 693-698 [doi]
• Efficient FPGA implementation of local binary convolutional neural networkAidyn Zhakatayev, Jongeun Lee. 699-704 [doi]
• Hardware-software co-design of slimmed optical neural networksZheng Zhao, Derong Liu 0002, Meng Li 0004, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan. 705-710 [doi]
• Software defined architectures for data analyticsVito Giovanni Castellana, Marco Minutoli, Antonino Tumeo, Marco Lattuada, Pietro Fezzardi, Fabrizio Ferrandi. 711-718 [doi]
• Runtime reconfigurable memory hierarchy in embedded scalable platformsDavide Giri, Paolo Mantovani, Luca P. Carloni. 719-726 [doi]
• XPPE: cross-platform performance estimation of hardware accelerators using machine learningHosein Mohammadi Makrani, Hossein Sayadi, Tinoosh Mohsenin, Setareh Rafatirad, Avesta Sasan, Houman Homayoun. 727-732 [doi]
• Addressing the issue of processing element under-utilization in general-purpose systolic deep learning acceleratorsBosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li. 733-738 [doi]
• ALook: adaptive lookup for GPGPU accelerationDaniel Peroni, Mohsen Imani, Tajana Rosing. 739-746 [doi]
• Collaborative accelerators for in-memory MapReduce on scale-up machinesAbraham Addisie, Valeria Bertacco. 747-753 [doi]
• Detailed routing by sparse grid graph and minimum-area-captured path searchGengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young. 754-760 [doi]
• Latency constraint guided buffer sizing and layer assignment for clock trees with useful skewNecati Uysal, Wen-Hao Liu, Rickard Ewetz. 761-766 [doi]