Horst A. Gieser - researchr alias

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Viewing Publication 1 - 13 from 13

2022

Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor SolutionsBernhard Lippmann, Ann-Christin Bette, Matthias Ludwig 0005, Johannes Mutter, Johanna Baehr, Alexander Hepp, Horst A. Gieser, Nicola Kovac, Tobias Zweifel, Martin Rasche, Oliver Kellermann. date 2022: 796-801 [doi]

2020

2019

Integrated flow for reverse engineering of nanoscale technologiesBernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb. aspdac 2019: 82-89 [doi]

2015

Electrostatic discharge sensitivity investigation on organic field-effect thin film transistorsTekfouy Lim, Horst A. Gieser, Luca Santarelli, Franco Cacialli. newcas 2015: 1-4 [doi]

2009

Investigating the CDM susceptibility of IC s at package and wafer level by capacitive coupled TLPHeinrich Wolf, Horst A. Gieser, Dirk Walter. mr, 49(12):1476-1481, 2009. [doi]

2006

Transient-induced latch-up test setup for wafer-level and package-levelDetlef Bonfert, Horst A. Gieser, Heinrich Wolf, M. Frank, A. Konrad, J. Schulz. mr, 46(9-11):1629-1633, 2006. [doi]

Study of CDM specific effects for a smart power input protection structureM. Etherton, N. Qu, J. Willemen, Wolfgang Wilkening, S. Mettler, M. Dissegna, R. Stella, L. Zullino, A. Andreini, Horst A. Gieser. mr, 46(5-6):666-676, 2006. [doi]

ESD Susceptibility of Submicron Air GapsHeinrich Wolf, Horst A. Gieser, Detlef Bonfert, Markus Hauser. mr, 46(9-11):1587-1590, 2006. [doi]

2005

2003

On-chip electrostatic discharge ESDHorst A. Gieser. mr, 43(7):985-986, 2003. [doi]

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