Table of Contents

• Flexible Thermal Conductance Model (TCM) for Efficient Thermal Simulation of 3-D ICs and PackagesShunxiang Lan, Min Tang, Jun Ma. 1-6 [doi]
• Hybrid Token Selector based Accelerator for ViTsAkshansh Yadav, Anadi Goyal, Palash Das. 1-7 [doi]
• Modeling the SL-LET Paradigm in AUTOSAR AdaptiveDavide Bellassai, Gerlando Sciangula, Claudio Scordino, Daniel Casini, Alessandro Biondi 0001. 1-7 [doi]
• VToT: Automatic Verilog Generation via LLMs with Tree of Thoughts PromptingYingjie Zhou, Renzhi Chen, Xinyu Li, Jingkai Wang, Zhigang Fang 0002, Bowei Wang, Wenqiang Bai, Qilin Cao, Lei Wang. 1-2 [doi]
• Post-Layout Automated Optimization for Capacitor Array in Digital-to-Time ConverterHefei Wang, Jianghao Su, Junhe Xue, Haoran Lyu, Junhua Zhang, Longyang Lin, Kai Chen, LiJuan Yang, Shenghua Zhou. 1-5 [doi]
• Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf OptimizerXiangfei Hu, Yuyang Ye 0001, Tinghuan Chen, Hao Yan 0002, Bei Yu 0001. 1-7 [doi]
• Multi-Partner Project: BIM-Powered Environmental Data Agent for More Resilient and Trustworthy Data CentersOguzhan Herkiloglu, Ali Serdar Atalay, Ibrahim Arif, Salih Ergün, Alper Kanak. 1-4 [doi]
• HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact EvaluationQuan Cheng, Wang Liao, Ruilin Zhang, Hao Yu 0001, Longyang Lin, Masanori Hashimoto. 1-7 [doi]
• Zebra: Leveraging Diagonal Attention Pattern for Vision Transformer AcceleratorSukhyun Han, Seongwook Kim, Gwangeun Byeon, Jihun Yoon, Seokin Hong. 1-7 [doi]
• LaRED: Efficient IR Drop Predictor with Layout-Preserving Rebuilder-Encoder-Decoder ArchitectureChengxuan Yu, Yanshuang Teng, Wenhao Dai, Yongjiang Li, Wei W. Xing, Xiao Wu, Dan Niu, Zhou Jin 0001. 1-7 [doi]
• Spatial Modeling with Automated Machine Learning and Gaussian Process Regression Techniques for Imputing Wafer Acceptance Test DataMing-Chun Wei, Chun-Wei Shen, Hsun-Ping Hsieh. 1-7 [doi]
• BMP-SD: Marrying Binary and Mixed-Precision Quantization for Efficient Stable Diffusion InferenceCheng Gu, Gang Li, Xiaolong Lin, Jiayao Ling, Jian Cheng, Xiaoyao Liang. 1-7 [doi]
• PFASware: Quantifying the Environmental Impact of Per- and Polyfluoroalkyl Substances (PFAS) in Computing SystemsMariam Elgamal, Abdulrahman Mahmoud, Gu-Yeon Wei, David Brooks 0001, Gage Hills. 1-2 [doi]
• Multi-Partner Project: Green.Dat.AI: A Data Spaces Architecture for Enhancing Green AI ServicesIoannis Chrysakis, Evangelos Agorogiannis, Nikoleta Tsampanaki, Michalis Vourtzoumis, Eva Chondrodima, Yannis Theodoridis, Domen Mongus, Ben Capper, Martin Wagner, Aris Sotiropoulos, Fábio André Coelho, Cláudia Vanessa Brito, Panos Protopapas, Despina Brasinika, Ioanna Fergadiotou, Christos Doulkeridis. 1-7 [doi]
• IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine LearningFeng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu 0006, Kang Zhao, Bei Yu 0001, Chuan Shi 0001. 1-7 [doi]
• LoopLynx: A Scalable Dataflow Architecture for Efficient LLM InferenceJianing Zheng, Gang Chen. 1-7 [doi]
• Ensuring Data Freshness for In-Storage Computing with Cooperative Buffer ManagerJin Xue, Yuhong Song, Yang Guo, Zili Shao. 1-7 [doi]
• SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level SparsityJingkui Yang, Mei Wen, Junzhong Shen, Jianchao Yang, Yasong Cao, Jun He, Minjin Tang, Zhaoyun Chen, Yang Shi. 1-7 [doi]
• Late Breaking Results: Physical Co-Design for Field-Coupled NanocomputingSimon Hofmann, Marcel Walter, Robert Wille. 1-2 [doi]
• EVASION: Efficient KV CAche CompreSsion vIa PrOduct QuaNtizationZongwu Wang, Fangxin Liu, Peng Xu, Qingxiao Sun, Junping Zhao, Li Jiang 0002. 1-2 [doi]
• Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC LockingHsiang-Chun Cheng, Ruijie Wang, TingTing Hwang. 1-7 [doi]
• ChemComp: Compiling and Computing with Chemical Reaction NetworksNicolas Bohm Agostini, Connah G. M. Johnson, William R. Cannon, Antonino Tumeo. 1-7 [doi]
• Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical ResultsMohammad Ebrahimabadi, Raphael Viera 0001, Sylvain Guilley, Jean-Luc Danger, Jean-Max Dutertre, Naghmeh Karimi. 1-2 [doi]
• Low-Latency Digital Feedback for Stochastic Quantum Calibration Using Cryogenic CMOSNathan Eli Miller, Laith A. Shamieh, Saibal Mukhopadhyay. 1-7 [doi]
• c2c-gem5: Full System Simulation of Cache-Coherent Chip-to-Chip InterconnectsLuis Bertran Alvarez, Ghassan Chehaibar, Stephen Busch, Pascal Benoit, David Novo. 1-7 [doi]
• Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic DeviceDebraj Kundu, Tsun-Ming Tseng, Shigeru Yamashita, Ulf Schlichtmann. 1-2 [doi]
• Slipstream: Semantic-Based Training Acceleration for Recommendation ModelsYassaman Ebrahimzadeh Maboud, Muhammad Adnan, Divya Mahajan 0001, Prashant J. Nair. 1-7 [doi]
• IterL2Norm: Fast Iterative L2-NormalizationChangmin Ye, Yonguk Sim, Youngchae Kim, SeongMin Jin, Doo Seok Jeong. 1-7 [doi]
• Accelerating Authenticated Block Ciphers via RISC-V Custom Cryptography InstructionsYuhang Qiu, Wenming Li, Tianyu Liu, Zhen Wang, Zhiyuan Zhang, Zhihua Fan, Xiaochun Ye, Dongrui Fan, Zhimin Tang. 1-7 [doi]
• SRing: A Sub-Ring Construction Method for Application-Specific Wavelength-Routed Optical NoCsZhidan Zheng, Meng Lian 0001, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 1-7 [doi]
• Federated Reinforcement Learning for Optimizing the Power Efficiency of Edge DevicesBenedikt Dietrich, Rasmus Müller-Both, Heba Khdr, Jörg Henkel. 1-7 [doi]
• A Lightweight CNN for Real-Time Pre-Impact Fall DetectionCristian Turetta, Muhammad Toqeer Ali, Florenc Demrozi, Graziano Pravadelli. 1-7 [doi]
• Lookup Table Refactoring: Towards Efficient Logarithmic Number System Addition for Large Language ModelsXinkuang Geng, Siting Liu 0001, Hui Wang 0023, Jie Han 0001, Honglan Jiang. 1-7 [doi]
• Static Global Register Allocation for Dynamic Binary TranslatorsNiko Zurstrabetaen, Nils Bosbach, Lennart M. Reimann, Rainer Leupers. 1-6 [doi]
• Late Breaking Results: Hyperdimensional Regression with Fine-Grained and Scalable Confidence-Based LearningJiseung Kim 0005, Hyunsei Lee, Tajana Rosing, Mohsen Imani, Yeseong Kim. 1-2 [doi]
• SACK: Enabling Environmental Situation-Aware Access Control for Vehicles in Linux KernelBoyan Chen, Qingni Shen, Lei Xue 0001, Jiarui She, Xiaolei Zhang, Xiapu Luo, Xin Zhang, Wei Chen 0006, Zhonghai Wu. 1-7 [doi]
• Continuous GNN-Based Anomaly Detection on Edge Using Efficient Adaptive Knowledge Graph LearningSanggeon Yun, Ryozo Masukawa, William Youngwoo Chung, Minhyoung Na, Nathaniel D. Bastian, Mohsen Imani. 1-7 [doi]
• RVEBS: Event-Based Sampling on RISC-VTiago Rocha, Nuno Neves 0002, Nuno Roma, Pedro Tomás, Leonel Sousa. 1-7 [doi]
• A CNN Compression Methodology for Layer-Wise Rank Selection Considering Inter-Layer InteractionsMilad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras, Iakovos Stamoulis. 1-7 [doi]
• PICBench: Benchmarking LLMs for Photonic Integrated Circuits DesignYuchao Wu, Xiaofei Yu, Hao Chen, Yang Luo, Yeyu Tong, Yuzhe Ma. 1-6 [doi]
• Amphi: Practical and Intelligent Data Prefetching for the First-Level CacheXuan Tang, Zicong Wang, Shuiyi He, Dezun Dong, Xiangke Liao. 1-2 [doi]
• DHD: Double Hard Decision Decoding Scheme for NAND Flash MemoryLanlan Cui, Yichuan Wang 0003, Renzhi Xiao, Miao Li, Xiaoxue Liu, Xinhong Hei 0001. 1-7 [doi]
• Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC)Bernhard Lippmann, Johanna Baehr 0001, Alexander Hepp, Horst A. Gieser. 1-7 [doi]
• RICH: Heterogeneous Computing for Real-Time Intelligent ControlJintao Chen, Yuankai Xu, Yinchen Ni, An Zou, Yehan Ma. 1-7 [doi]
• Multi-Partner Project: Orchestrating Deployment and Real-Time Monitoring - NEPHELE Multi-Cloud EcosystemManolis Katsaragakis, Orfeas Filippopoulos, Christos Sad, Dimosthenis Masouros, Dimitrios Spatharakis, Ioannis Dimolitsas, Nikos Filinis, Anastasios Zafeiropoulos, Kostas Siozios, Dimitrios Soudris, Symeon Papavassiliou. 1-6 [doi]
• SCALES: Boost Binary Neural Network for Image Super-Resolution with Efficient ScalingsRenjie Wei, Zechun Liu, Yuchen Fan, Runsheng Wang, Ru Huang 0001, Meng Li 0004. 1-7 [doi]
• ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICsAfolabi Ige, Jennifer Hasler. 1-6 [doi]
• MEMHD: Memory-Efficient Multi-Centroid Hyperdimensional Computing for Fully-Utilized In-Memory Computing ArchitecturesDo Yeong Kang, Yeong Hwan Oh, Chanwook Hwang, Jinhee Kim, Kang Eun Jeon, Jong Hwan Ko. 1-7 [doi]
• SEDG: Stitch-Compatible End-to-End Layout Decomposition Based on Graph Neural NetworkYifan Guo, Jiawei Chen, Yexin Li, Yunxiang Zhang, Qing Zhang 0008, Yuhang Zhang 0008, Yongfu Li 0002. 1-7 [doi]
• INTO-OA: Interpretable Topology Optimization for Operational AmplifiersJinyi Shen, Fan Yang 0001, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 1-7 [doi]
• ADAPT-pNC: Mitigating Device Variability and Sensor Noise in Printed Neuromorphic Circuits with SO Adaptive Learnable FiltersTara Gheshlaghi, Priyanjana Pal, Haibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. 1-7 [doi]
• KalmMind: A Configurable Kalman Filter Design Framework for Embedded Brain-Computer InterfacesGuy Eichler, Joseph Zuckerman, Luca P. Carloni. 1-2 [doi]
• WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary PredictionJiawei Liu 0006, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu 0001, Bei Yu 0001, Chuan Shi 0001. 1-7 [doi]
• DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed PlacementChuyu Wang, Ke Hu, Fan Yang 0001, Keren Zhu 0001, Xuan Zeng 0001. 1-7 [doi]
• A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGAKentaroh Katoh, Toru Nakura, Haruo Kobayashi 0001. 1-2 [doi]
• Column-wise Quantization of Weights and Partial Sums for Accurate and Efficient Compute-In-Memory AcceleratorsJiyoon Kim, Kang Eun Jeon, Yulhwa Kim, Jong Hwan Ko. 1-7 [doi]
• Enabling SNN-Based Near-MEA Neural Decoding with Channel Selection: An Open-HW ApproachGianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni. 1-7 [doi]
• Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement LearningDavide Basso, Luca Bortolussi, Mirjana S. Videnovic-Misic, Husni Habal. 1-7 [doi]
• Late Breaking Results: Towards Efficient Formal Verification of Dot Product ArchitecturesLennart Weingarten, Kamalika Datta, Rolf Drechsler. 1-2 [doi]
• Coala: Coalescion-Based Acceleration of Polynomial Multiplication for GPU ExecutionHomer Gamil, Oleg Mazonka, Michail Maniatakos. 1-7 [doi]
• Locality-Aware Data Placement for NUMA Architectures: Data Decoupling and Asynchronous ReplicationShuhan Bai, Haowen Luo, Burong Dong, Jian Zhou, Fei Wu. 1-7 [doi]
• Designing Secure Space SystemsZain Alabedin Haj Hammadeh, Mohammad Hamad, Andrzej Olchawa, Milenko Starcik, Ricardo Fradique, Stefan Langhammer, Manuel Hoffmann, Florian Göhler, Daniel Lüdtke, Michael Felderer, Sebastian Steinhorst. 1-10 [doi]
• Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJITYe Cai 0001, Chuyu Zheng, Wei He, Dan Tang. 1-2 [doi]
• SHWCIM: A Scalable Heterogeneous Workload Computing-in-Memory ArchitectureYanfeng Yang, Yi Zou, Zhibiao Xue, Liuyang Zhang. 1-7 [doi]
• Decentralizing IoT Data Processing: The Rise of Blockchain-Based SolutionsGiuseppe Spadavecchia, Marco Fiore 0002, Marina Mongiello, Daniela De Venuto. 1-2 [doi]
• Compromising the Intelligence of Modern DNNs: On the Effectiveness of Targeted RowPressRanyang Zhou, Jacqueline T. Liu, Sabbir Ahmed, Shaahin Angizi, Adnan Siraj Rakin. 1-7 [doi]
• TrackScorer: Skyrmion Logic-in-Memory Accelerator for Tree-Based Ranking ModelsElijah Seth Cishugi, Sebastian Buschjäger, Martijn Noorlander, Marco Ottavi, Kuan-Hsun Chen. 1-7 [doi]
• SafeLight: Enhancing Security in Optical Convolutional Neural Network AcceleratorsSalma Afifi, Ishan G. Thakkar, Sudeep Pasricha. 1-7 [doi]
• Enabling Memory-Efficient On-Device Learning via Dataset CondensationGelei Xu, Ningzhi Tang, Jun Xia 0003, Ruiyang Qin, Wei Jin, Yiyu Shi 0001. 1-7 [doi]
• Application of Formal Methods (SAT/SMT) to the Design of Constrained CodesSunil Sudhakaran, Clark W. Barrett, Mark Horowitz. 1-7 [doi]
• Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge DevicesJing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang. 1-7 [doi]
• RoTA: Rotational Torus Accelerator for Wear Leveling of Neural Processing ElementsTaesoo Lim, Hyeonjin Kim, Jingu Park, Bogil Kim, William J. Song. 1-7 [doi]
• Multi-Partner Project: Shaping the Vehicle of the Future - How FEDERATE and HAL4SDV are Steering Europe's Software-Defined Vehicle EcosystemMichael Paulweber, Andreas Eckel, Paolo Azzoni. 1-4 [doi]
• PESEC - A Simple Power-Efficient Single Error Correcting Coding Scheme for RRAMShlomo Engelberg, Osnat Keren. 1-7 [doi]
• Transistor Aging and Circuit Reliability at Cryogenic TemperaturesJavier Diaz-Fortuny, Vishal Nayar. 1-4 [doi]
• Compatibility Graph Assisted Automatic Hardware Trojan Insertion FrameworkGaurav Kumar, Ashfaq Hussain Shaik, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat. 1-7 [doi]
• Multi-Partner Project: Sustainable Textile Electronics (STELEC)Bo Zhou 0005, Mengxi Liu, Sizhen Bian, Daniel Geibetaler, Paul Lukowicz, José Miranda, Jonathan Dan, David Atienza, Mohamed Amine Riahi, Norbert Wehn, Russel N. Torah, Sheng Yong, Jidong Liu, Stephen P. Beeby, Magdalena Kohler, Berit Greinke, Junchun Yu, Vincent Nierstrasz, Leila Sheldrick, Rebecca Stewart, Tommaso Nieri, Matteo Maccanti, Daniele Spinelli. 1-5 [doi]
• TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUsDiyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini. 1-7 [doi]
• SACPlace: Multi-Agent Deep Reinforcement Learning for Symmetry-Aware Analog Circuit PlacementLei Cai, Guojing Ge, Guibo Zhu, Jixin Zhang, Jinqiao Wang, Bowen Jia, Ning Xu 0006. 1-7 [doi]
• Fast Machine Learning Based Prediction for Temperature Simulation Using Compact ModelsMohammadamin HajiKhodaverdian, Sherief Reda, Ayse K. Coskun. 1-2 [doi]
• An eDRAM Digital In-Memory Neural Network Accelerator for High-Throughput and Extended Data Retention TimeInhwan Lee, Jehun Lee, Jaeyong Jang, Jae-Joon Kim. 1-7 [doi]
• LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog GenerationDingyang Zou, Gaoche Zhang, Kairui Sun, Zhe Wen, Meiqi Wang, Zhongfeng Wang 0001. 1-2 [doi]
• Security Assertions for Trusted Execution EnvironmentsHasini Witharana, Hansika Weerasena, Prabhat Mishra 0001. 1-6 [doi]
• Automatic Routing for Photonic Integrated Circuits Under Delay Matching ConstraintsYuchao Wu, Weilong Guan, Yeyu Tong, Yuzhe Ma. 1-2 [doi]
• DEAR-PIM: Processing-in-Memory Architecture with Disaggregated Execution of All-bank RequestsJungi Hyun, Minseok Seo, Seongho Jeong, Hyuk-Jae Lee, Xuan Truong Nguyen. 1-7 [doi]
• ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary QuantizationRuiqi Chen 0001, Jiayu Liu, Shidi Tang, Yang Liu, Yanxiang Zhu, Ming Ling, Bruno da Silva. 1-6 [doi]
• From Gates to SDCs: Understanding Fault Propagation Through the Compute StackOdysseas Chatzopoulos, George Papadimitriou 0001, Dimitris Gizopoulos, Harish Dattatraya Dixit, Sriram Sankar. 1-7 [doi]
• Identification of Hazardous Driving Scenarios Using Cross-Channel Safety Performance IndicatorsC. A. J. Hanselaar, M. M. Selva Kumar, Yuting Fu, Andrei Terechko, R. R. Venkatesha Prasad, Emilia Silvas. 1-7 [doi]
• Nanoelectromechanical Binary Comparator for Edge-Computing ApplicationsVictor Marot, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Elliott Worsey, Roshan Weerasekera, Dinesh Pamunuwa. 1-7 [doi]
• MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D ICTianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang 0001. 1-7 [doi]
• SBQ: Exploiting Significant Bits for Efficient and Accurate Post-Training DNN QuantizationJiayao Ling, Gang Li, Qinghao Hu, Xiaolong Lin, Cheng Gu, Jian Cheng 0001, Xiaoyao Liang. 1-7 [doi]
• Deterministic Fault-Tolerant State Preparation for Near-Term Quantum Error Correction: Automatic Synthesis Using Boolean SatisfiabilityLudwig Schmid, Tom Peham, Lucas Berent, Markus Müller, Robert Wille. 1-7 [doi]
• ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution RedundancyJiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye 0001, Huawei Li 0001, Xiaowei Li 0001. 1-7 [doi]
• Improving Software Reliability with Rust: Implementation for Enhanced Control Flow Checking MethodsJacopo Sini, Mohammadreza Amel Solouki, Massimo Violante, Giorgio Di Natale. 1-7 [doi]
• Self-Adaptive Ising Machines for Constrained OptimizationCorentin Delacour. 1-7 [doi]
• NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page TableQingcai Jiang, Buxin Tu, Hong An. 1-7 [doi]
• Low-Rank Compression for IMC ArraysKang Eun Jeon, Johnny Rhe, Jong Hwan Ko. 1-7 [doi]
• A DRAM-Based Processing-in-Memory Accelerator for Privacy-Protecting Machine LearningBokyung Kim. 1-2 [doi]
• Towards Reliable Systems: A Scalable Approach to AXI4 Transaction MonitoringChaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi. 1-7 [doi]
• Segment-Wise Accumulation: Low-Error Logarithmic Domain Computing for Efficient Large Language Model InferenceXinkuang Geng, Yunjie Lu, Hui Wang 0023, Honglan Jiang. 1-7 [doi]
• Late Breaking Results: Improving Deep SNNs with Gradient Clipping and Noise Exploitation in Neuromorphic DevicesSeongsik Park, Jongkil Park 0001, Hyun Jae Jang, Jaewook Kim, YeonJoo Jeong, Gye Weon Hwang, Inho Kim, Jong-Keuk Park, Kyeong-Seok Lee, Suyoun Lee. 1-2 [doi]
• HiDP: Hierarchical DNN Partitioning for Distributed Inference on Heterogeneous Edge PlatformsZain Taufique, Aman Vyas, Antonio Miele, Pasi Liljeberg, Anil Kanduri. 1-7 [doi]
• SAFELOC: Overcoming Data Poisoning Attacks in Heterogeneous Federated Machine Learning for Indoor LocalizationAkhil Singampalli, Danish Gufran, Sudeep Pasricha. 1-7 [doi]
• Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUsSeverin Bochem, Victor J. B. Jung, Arpan Suravi Prasad, Francesco Conti 0001, Luca Benini. 1-7 [doi]
• TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based CryptographyAlessandra Dolmeta, Stefano Di Matteo, Emanuele Valea, Mikael Carmona, Antoine Loiseau, Maurizio Martina, Guido Masera. 1-7 [doi]
• SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation ExtensionsSimone Manoni, Paul Scheffler, Luca Zanatta, Andrea Acquaviva, Luca Benini, Andrea Bartolini. 1-7 [doi]
• TPC-GAN: Batch Topology Synthesis for Performance-Compliant Operational Amplifiers Using Generative Adversarial NetworksYuhao Leng, Jinglin Han, Yining Wang, Peng Wang 0022. 1-7 [doi]
• Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and ChallengesAmit Ranjan Trivedi, Sina Tayebati, Hemant Kumawat, Nastaran Darabi, Divake Kumar, Adarsh Kumar Kosta, Yeshwanth Venkatesha, Dinithi Jayasuriya, Nethmi Jayasinghe, Priyadarshini Panda, Saibal Mukhopadhyay, Kaushik Roy 0001. 1-10 [doi]
• PEARL: FPGA-Based Reinforcement Learning Acceleration with Pipelined Parallel EnvironmentsJiayi Li, Hongxiao Zhao, Wenshuo Yue, Yihan Fu, Daijing Shi, Anjunyi Fan, Yuchao Yang, Bonan Yan. 1-7 [doi]
• Towards Fast Automatic Design of Silicon Dangling Bond LogicJan Drewniok, Marcel Walter, Samuel Sze Hang Ng, Konrad Walus, Robert Wille. 1-2 [doi]
• Integer Unit-Based Outlier-Aware LLM Accelerator Preserving Numerical Accuracy of FP-FP GEMMJehun Lee, Jae-Joon Kim. 1-7 [doi]
• Efficient Hold Buffer Optimization by Supply Noise-Aware Dynamic Timing AnalysisLishuo Deng, Changwei Yan, Cai Li, Zhuo Chen, Weiwei Shan. 1-7 [doi]
• Late Breaking Results: Automatic Anomaly Detection Method in Physical Unclonable Functions using Data Mining TechniquesMohammad Reza Heidari Iman, Sergio Vinagrero Gutierrez, Elena Ioana Vatajelu, Giorgio Di Natale. 1-2 [doi]
• Improving Figures of Merit for Quantum Circuit CompilationPatrick Hopf, Nils Quetschlich, Laura Brandon Schulz, Robert Wille. 1-7 [doi]
• Are LLMs Ready for Practical Adoption for Assertion Generation?Vaishnavi Pulavarthi, Deeksha Nandal, Soham Dan, Debjit Pal. 1-7 [doi]
• Timing-Driven Global Placement by Efficient Critical Path ExtractionYunqi Shi, Siyuan Xu, Shixiong Kai, Xi Lin, Ke Xue 0001, Mingxuan Yuan, Chao Qian 0001. 1-7 [doi]
• EF-IMR: Embedded Flash with Interlaced Magnetic Recording TechnologyChenlin Ma, Xiaochuan Zheng, Kaoyi Sun, Tianyu Wang 0009, Yi Wang 0003. 1-2 [doi]
• Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel TransistorEduardo Ortega, Jungyoun Kwak, Shimeng Yu, Krishnendu Chakrabarty. 1-7 [doi]
• DisPEED: Distributing Packet flow analyses in a swarm of heterogeneous EmbEddeD platformsLouis Morge-Rollet, Camélia Slimani, Laurent Lemarchand, Frédéric Le Roy, David Espes, Jalil Boukhobza. 1-7 [doi]
• One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDsShaoqi Li, Tianyu Wang 0009, Yongbiao Zhu, Chenlin Ma, Yi Wang 0003, Zhaoyan Shen, Zili Shao. 1-2 [doi]
• Late Breaking Results: Energy-Efficient Printed Machine Learning Classifiers with Sequential SVMsSpyridon Besias, Ilias Sertaridis, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis 0001. 1-2 [doi]
• NORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory AcceleratorsYayue Hou, Hsinyu Tsai, Kaoutar El Maghraoui, Tayfun Gokmen, Geoffrey W. Burr, Liu Liu. 1-7 [doi]
• Exploiting Boosting in Hyperdimensional Computing for Enhanced Reliability in HealthcareSungHeon Jeong 0001, Hamza Errahmouni Barkam, Sanggeon Yun, Yeseong Kim, Shaahin Angizi, Mohsen Imani. 1-7 [doi]
• Arbiter: Alleviating Concurrent Write Amplification in Persistent MemoryBolun Zhu, Yu Hua 0001. 1-7 [doi]
• DEAR: Dependable 3D Architecture for Robust DNN TrainingAshish Reddy Bommana, Farshad Firouzi, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 1-7 [doi]
• CLAIRE: Composable Chiplet Libraries for AI InferencePragnya Sudershan Nalla, Emad Haque, Yaotian Liu, Sachin S. Sapatnekar, Jeff Zhang 0001, Chaitali Chakrabarti, Yu Cao 0001. 1-7 [doi]
• Late Breaking Results: Is Reconfigurable-Based Obfuscation Secure?Zain Ul Abideen 0002, Levent Aksoy, Samuel Pagliarini. 1-2 [doi]
• A Practical Learning-Based FTL for Memory Constrained Mobile Flash StorageZelin Du, Kecheng Huang, Tianyu Wang 0009, Xin Yao, Renhai Chen, Zili Shao. 1-7 [doi]
• Adaptive Branch-and-Bound Tree Exploration for Neural Network VerificationKota Fukuda, Guanqin Zhang, Zhenya Zhang, Yulei Sui, Jianjun Zhao 0001. 1-7 [doi]
• Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality SystemsSafin Bayes, Mohamed Hassan 0002. 1-7 [doi]
• FloppyFloat: An Open Source Floating Point Library for Instruction Set SimulatorsNiko Zurstraßen, Nils Bosbach, Rainer Leupers. 1-6 [doi]
• Side-Channel Collision Attacks Against ASCONHao Zhang, Yiwen Gao 0001, Yongbin Zhou, Jingdian Ming. 1-6 [doi]
• Grafted Trees Bear Better Fruit: An Improved Multiple-Valued Plaintext-Checking Side-Channel Attack Against KyberJinnuo Li, Chi Cheng, Muyan Shen, Peng Chen, Qian Guo 0001, Dongsheng Liu, Liji Wu, Jian Weng 0001. 1-7 [doi]
• 2r: Unifying DVFS and Early-Exit for Embedded AI Inference via Reinforcement LearningYuting He, Jingjin Li, Chengtai Li, Qingyu Yang, Zheng Wang, Heshan Du, Jianfeng Ren, Heng Yu 0001. 1-7 [doi]
• An Imitation Augmented Reinforcement Learning Framework for CGRA Design Space ExplorationLiangji Wu, Shuaibo Huang, Ziqi Wang, Shiyang Wu, Yang Chen, Hao Yan 0002, Longxing Shi. 1-7 [doi]
• SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge DevicesYipu Zhang, Jiawei Liang, Jian Peng, Jiang Xu 0001, Wei Zhang 0012. 1-7 [doi]
• HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL EngineersYiyao Yang, Fu Teng, Pengju Liu, MengNan Qi, Chenyang Lv, Ji Li, Xuhong Zhang 0002, Zhezhi He. 1-7 [doi]
• DOTS: DRAM-PIM Optimization for Tall and Skinny GEMM Operations in LLM InferenceGyeonghwan Park, SangHyeok Han, Byungkuk Yoon, Jae-Joon Kim. 1-2 [doi]
• Evaluating Compiler-Based Reliability with Radiation Fault InjectionDavide Baroffio, Tomas Antonio Lopez, Federico Reghenzani, William Fornaciari. 1-2 [doi]
• C2C: A Framework for Critical Token Classification in Transformer-Based Inference SystemsMyeongjae Jang, Jesung Kim, Haejin Nam, Sihyun Kim, Soontae Kim. 1-2 [doi]
• Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2colMd Mizanur Rahaman Nayan, Ritik Raj, Shaik Gouse Basha, Tushar Krishna, Azad J. Naeemi. 1-7 [doi]
• Image Computation for Quantum Transition SystemsXin Hong, Dingchao Gao, Sanjiang Li, Shenggang Ying, Mingsheng Ying. 1-7 [doi]
• LT-OAQ: Learnable Threshold Based Outlier-Aware Quantization and its Energy-Efficient Accelerator for Low-Precision On-Chip TrainingQinkai Xu, Yijin Liu, Yuan Meng, Yang Chen, Yunlong Mao, Li Li, Yuxiang Fu. 1-6 [doi]
• Ferroelectric-Superconducting Synergy for Future ComputingShamiul Alam, Ahmedullah Aziz. 1-6 [doi]
• MCTA: A Multi-Stage Co-Optimized Transformer Accelerator with Energy-Efficient Dynamic Sparse OptimizationHeng Liu, Ming Han, Jin Wu, Ye Wang, Jian Dong. 1-7 [doi]
• CISGraph: A Contribution-Driven Accelerator for Pairwise Streaming Graph AnalyticsSongyu Feng, Mo Zou, Tian Zhi, Zidong Du. 1-7 [doi]
• FVEval: Understanding Language Model Capabilities in Formal Verification of Digital HardwareMinwoo Kang, Mingjie Liu, Ghaith Bany Hamad, Syed M. Suhaib, Haoxing Ren. 1-6 [doi]
• PS-GS: Group-Wise Parallel Rendering with Stage-Wise Complexity Reductions for Real-Time 3D Gaussian SplattingJoongho Jo, Jongsun Park 0001. 1-7 [doi]
• MAPS: Multi-Fidelity AI-Augmented Photonic Simulation and Inverse Design InfrastructurePingchuan Mal, Zhengqi Gao, Meng Zhang, Haoyu Yang, Mark Ren, Z. Rena Huang, Duane S. Boning, Jiaqi Gu 0002. 1-6 [doi]
• Testing Robustness of Homomorphically Encrypted Split Model LLMsLars Wolfgang Folkerts, Nektarios Georgios Tsoutsos. 1-7 [doi]
• CIM-Based Parallel Fully FFNN Surface Code High-Level Decoder for Quantum Error CorrectionHao Wang, Erjia Xiao, Songhuan He, Zhongyi Ni, LingFeng Zhang, Xiaokun Zhan, Yifei Cui, Jinguo Liu, Cheng Wang, Zhongrui Wang, Renjing Xu. 1-2 [doi]
• Practical MU-MIMO Detection and LDPC Decoding Through Digital AnnealingPo-Shao Chen, Wei Tang, Zhengya Zhang. 1-7 [doi]
• Algorithm-Hardware Co-Design of a Unified Accelerator for Non-Linear Functions in TransformersHaonan Du, Chenyi Wen, Zhengrui Chen, Li Zhang 0021, Qi Sun 0002, Zheyu Yan, Cheng Zhuo. 1-7 [doi]
• Generating and Predicting Output Perturbations in Image SegmentersMatthew Bozoukov, Nguyen Anh Vu Doan, Bryan Donyanavard. 1-6 [doi]
• AIRCHITECT v2: Learning the Hardware Accelerator Design Space Through Unified RepresentationsJamin Seo, Akshat Ramachandran, Yu-Chuan Chuang, Anirudh Itagi, Tushar Krishna. 1-7 [doi]
• HAAN: A Holistic Approach for Accelerating Normalization Operations in Large Language ModelsTianfan Peng, Tianhua Xia, Jiajun Qin, Sai Qian Zhang. 1-7 [doi]
• Multi-Partner Project: A Model-Driven Engineering Framework for Federated Digital Twins of Industrial Systems (MATISSE)Alessio Bucaioni, Romina Eramo, Luca Berardinelli, Hugo Bruneliere, Benoît Combemale, Djamel Eddine Khelladi, Vittoriano Muttillo, Andrey Sadovykh, Manuel Wimmer. 1-6 [doi]
• Exact Schedulability Analysis for Limited-Preemptive Parallel Applications Using Timed Automata in UPPAALJonas Hansen, Srinidhi Srinivasan, Geoffrey Nelissen, Kim G. Larsen. 1-7 [doi]
• Hardware/Software Co-Analysis for Worst Case Execution Time BoundsCan Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jörg Henkel. 1-2 [doi]
• MegaRoute: Universal Automated Large-Scale PCB Routing Method with Adaptive Step-Size SearchHaiyun Li, Jixin Zhang. 1-7 [doi]
• ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different TechnologiesTaehoon Kim, Minjeong Kim, Hankyu Chi, Byungjun Kang, Eunji Song, Woo-seok Choi. 1-7 [doi]
• A Synthesizable Thyristor-Like Leakage-Based True Random Number GeneratorSeohyun Kim, Jang-Hyun Kim, Jongmin Lee. 1-7 [doi]
• A Performance Analysis of Chiplet-Based SystemsNeethu Bal Mallya, Panagiotis Strikos, Bhavishya Goel, Ahsen Ejaz, Ioannis Sourdis. 1-7 [doi]
• A Comprehensive Inductance-Aware Modeling Approach to Power Distribution Network in Heterogeneous 3D Integrated CircuitsQuansen Wang, Vasilis F. Pavlidis, Yuanqing Cheng. 1-2 [doi]
• ASNPC: An Automated Generation Framework for SNN and Neuromorphic Processor Co-DesignXiangyu Wang, Yuan Li, Zhijie Yang, Chao Xiao, Xun Xiao, Renzhi Chen, Weixia Xu, Lei Wang. 1-7 [doi]
• UPAQ: A Framework for Real-Time and Energy-Efficient 3D Object Detection in Autonomous VehiclesAbhishek Balasubramaniam, Febin P. Sunny, Sudeep Pasricha. 1-7 [doi]
• Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence ChecksJohannes Geier, Leonidas Kontopoulos, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 1-7 [doi]
• RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code GenerationLakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam, Ramesh Karri, Michail Maniatakos, Ozgur Sinanoglu, Johann Knechtel. 1-7 [doi]
• Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet TechnologyYukai Chen, Subrat Mishra, Julien Ryckaert, Dwaipayan Biswas, James Myers. 1-2 [doi]
• SparDR: Accelerating Unstructured Sparse DNN Inference via Dataflow OptimizationWei Wang, Hongxu Jiang, Runhua Zhang 0002, Yongxiang Cao, Yaochen Han. 1-7 [doi]
• LowGradQ: Adaptive Gradient Quantization for Low-Bit CNN Training via Kernel Density Estimation-Guided Thresholding and Hardware-Efficient Stochastic Rounding UnitSangbeom Jeong, SeungIl Lee, Hyun Kim. 1-2 [doi]
• HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption CompilerWeidong Yang, Shuya Ji, Jianfei Jiang 0001, Naifeng Jing, Qin Wang 0009, Zhigang Mao, Weiguang Sheng. 1-6 [doi]
• Multi-Partner Project: Smart Sensor Analog Front-Ends Powered by Emerging Reconfigurable Devices (SENSOTERIC)Giulio Galderisi, Andreas Kramer, Andreas Fuchsberger, Jose Maria Gonzalez-Medina, Yuxuan He, Lee-Chi Hung, Marrit Jen Hong Li, Julian Kulenkampff, Maximilian Reuter, Lukas Wind, Masiar Sistani, Thomas Mikolajick, Bruno Neckel Wesling, Marina Deng, Cristell Maneux, Pieter Harpe, Sonia Prado-López, Oskar Baumgartner, Chhandak Mukherjee, Eugenio Cantatore, Sandro Carrara, Klaus Hofmann, Walter M. Weber, Jens Trommer. 1-4 [doi]
• Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving PerceptionMohanad Odema, Luke Chen, Hyoukjun Kwon, Mohammad Abdullah Al Faruque. 1-7 [doi]
• Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout SynthesisSiou-Sian Lin, Shih-Yu Chen, Yu-Ping Huang, Tzu-Chuan Lin, Hung-Ming Chen, Wei-Zen Chen. 1-7 [doi]
• Multi-Partner Project: Secure Hardware Accelerated Data Analytics for 6G Networks: The PRIVATEER ApproachIlias Papalamprou, Aimilios Leftheriotis, Apostolis Garos, Georgios Gardikis, Maria Christopoulou, George Xilouris, Lampros Argyriou, Antonia Karamatskou, Nikolaos Papadakis, Emmanouil Kalotychos, Nikolaos Chatzivasileiadis, Dimosthenis Masouros, George Theodoridis, Dimitrios Soudris. 1-4 [doi]
• Exploring Dendritic Computation in Bio-Inspired Architectures for Dynamic ProgrammingAnup Das. 1-6 [doi]
• High-Throughput SAT SamplingArash Ardakani, Minwoo Kang, Kevin He, Qijing Huang 0001, John Wawrzynek. 1-7 [doi]
• Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic ComputingMahdi Benkhelifa, Shivendra Singh Parihar, Anirban Kar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch. 1-6 [doi]
• Cool3D: Cost-Optimized and Efficient Liquid Cooling for 3D Integrated CircuitsJing Li, Bingrui Zhang, Yuquan Sun, Wei Xing, Yuanqing Cheng. 1-7 [doi]
• SPIRE: Inferring Hardware Bottlenecks from Performance Counter DataNicholas Wendt, Mahesh Ketkar, Valeria Bertacco. 1-7 [doi]
• CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL DesignRuidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li 0005. 1-7 [doi]
• A Baseline Framework for the Qualification of LTL Specification MinersSamuele Germiniani, Daniele Nicoletti, Graziano Pravadelli. 1-7 [doi]
• GLEAM: Graph-Based Learning Through Efficient Aggregation in MemoryAndrew McCrabb, Ivris Raymond, Valeria Bertacco. 1-7 [doi]
• NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic ComputingYi Zhong, Zilin Wang, Yipeng Gao, Xiaoxin Cui, Xing Zhang 0002, Yuan Wang 0001. 1-7 [doi]
• A Unified Vector Processing Unit for Fully Homomorphic EncryptionJiangbin Dong, Xinhua Chen, Mingyu Gao 0001. 1-7 [doi]
• FairXbar: Improving the Fairness of Deep Neural Networks with Non-Ideal in-Memory Computing HardwareSohan Salahuddin Mugdho, Yuanbo Guo, Ethan G. Rogers, Weiwei Zhao, Yiyu Shi, Cheng Wang. 1-7 [doi]
• Multi-Partner Project: CyberSecDome - Framework for Secure, Collaborative, and Privacy-Aware Incident Handling for Digital InfrastructureMohammad Hamad, Michael Kühr, Haralambos Mouratidis, Eleni-Maria Kalogeraki, Christos Gizelis, Dimitris Papanikas, Athanasios Bountioukos-Spinaris, Charilaos Skandylas, Evangelos Raptis, Andreas Alexopoulos, Grigorios Chrysos 0001, Mina Marmpena, Sevasti Politi, Konstantinos Lieros, Papagiannopoulos Nikolaos, Iordanis Xanthopoulos, Spyros Papastergiou, Sotiris Ioannidis, Mikael Asplund, Marc-Oliver Pahl, Sebastian Steinhorst. 1-7 [doi]
• qGDP: Quantum Legalization and Detailed Placement for Superconducting Quantum ComputersJunyao Zhang, Guanglei Zhou, Feng Cheng, Jonathan Ku, Qi Ding, Jiaqi Gu 0002, Hanrui Wang 0002, Hai Helen Li, Yiran Chen 0001. 1-7 [doi]
• Coupling Neural Networks and Physics Equations For Li-Ion Battery State-of-Charge PredictionGiovanni Pollo, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari. 1-7 [doi]
• SolarML: Optimizing Sensing and Inference for Solar-Powered TinyML PlatformsHao Liu, Qing Wang 0007, Marco Zuniga. 1-7 [doi]
• A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural NetworksXiaolu Hu, Xinkuang Geng, Zhigang Mao, Jie Han 0001, Honglan Jiang. 1-7 [doi]
• Accelerating Oblivious Transfer with a Pipelined ArchitectureXiaolin Li, Wei Yan, Hongwei Liu, Yong Zhang, Qinfen Hao, Yong Liu, Ninghui Sun. 1-2 [doi]
• Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT)Marko S. Andjelkovic, Fabian Vargas 0001, Milos Krstic, Luigi Dilillo, Alain Michez, Frederic Wrobel, Davide Bertozzi, Mikel Luján, Christos Georgakidis, Nikolaos Chatzivangelis, Katerina Tsilingiri, Nikolaos Zazatis, Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Christos P. Sotiriou. 1-6 [doi]
• Speeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay SymmetryTaehwan Kim, Jongsun Park 0001. 1-2 [doi]
• Maximum Fanout-Free Window Enumeration: Towards Multi-Output Sub-Structure SynthesisRuofei Tang, Xuliang Zhu, Lei Chen, Xing Li, Xin Huang 0001, Mingxuan Yuan, Jianliang Xu. 1-7 [doi]
• Bi-Level Optimization Accelerated DRC-Aware Physical Design Automation for Photonic DevicesHao Chen, Yuzhe Ma, Yeyu Tong. 1-7 [doi]
• MPTorch-FPGA: A Custom Mixed-Precision Framework for FPGA-Based DNN TrainingSami Ben Ali, Silviu-Ioan Filip, Olivier Sentieys, Guy G. Lemieux. 1-7 [doi]
• Improving Address Translation in Tagless DRAM Cache by Caching PTE PagesOsang Kwon, Yongho Lee, Seokin Hong. 1-7 [doi]
• Co-Design of Sustainable Embedded Systems-on-ChipJan Spieck, Dominik Walter, Jan Waschkeit, Jürgen Teich. 1-2 [doi]
• Wire-Bonding Finger Placement for FBGA Substrate Layout Design with Finger Orientation ConsiderationYu-En Lin, Yi-Yu Liu. 1-6 [doi]
• HyIMC: Analog-Digital Hybrid In-Memory Computing SoC for High-Quality Low-Latency Speech EnhancementWanru Mao, Hanjie Liu, Guangyao Wang, Tianshuo Bai, Jingcheng Gu, Han Zhang, Xitong Yang, Aifei Zhang, Xiaohang Wei, Meng Wang, Wang Kang 0001. 1-2 [doi]
• RGHT-Q: Reconfigurable GEMM Unit for Heterogeneous-Homogeneous Tensor QuantizationSeungho Lee, Donghyun Nam, Jeongwoo Park. 1-2 [doi]
• Specification Mining Facing Generative AIGoerschwin Fey, Harry Foster, Tara Ghasempuri, Badri Gopalan, Jörg Müller, Manish Pandey. 1 [doi]
• Optimal Synthesis of Memristive Mixed-Mode CircuitsIlia Polian, Xianyue Zhao, Li-Wei Chen 0001, Felix Bayhurst, Ziang Chen, Heidemarie Schmidt, Nan Du 0004. 1-7 [doi]
• Circuits in a Box: Computing High-Dimensional Performance Spaces for Analog Integrated CircuitsBenedikt Ohse, Jürgen Kampe, Christopher Schneider. 1-7 [doi]
• LiGNN: Accelerating GNN Training Through Locality-Aware DropoutGongjian Sun, Mingyu Yan, Dengke Han, Runzhen Xue, Xiaochun Ye, Dongrui Fan. 1-7 [doi]
• Late Breaking Results: AFS: Improving Accuracy of Quantized Mamba via Aggressive Forgetting StrategyZhouquan Liu, Libo Huang, Ling Yang, Gang Chen, Wei Liu, Mingche Lai, Yongwen Wang. 1-2 [doi]
• FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic EncryptionTengyu Zhang, Yufei Xue, Ling Liang, Zhen Gu, Yuan Wang 0001, Runsheng Wang, Ru Huang 0001, Meng Li 0004. 1-7 [doi]
• Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect ConsiderationYu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Peng-Wen Chen, Po-Yu Chen, Hao-Yun Chen, Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Chang. 1-7 [doi]
• Late Breaking Results: Approximated LUT-Based Neural Networks for FPGA Accelerated InferenceXuqi Zhu, Jiacheng Zhu, Huaizhi Zhang, Tamim M. Al-Hasan, Klaus D. McDonald-Maier, Xiaojun Zhai. 1-2 [doi]
• A System Level Performance Evaluation for Superconducting Digital SystemsJoyjit Kundu, Debjyoti Bhattacharjee, Nathan Josephsen, Ankit Pokhrel, Udara De Silva, Wenzhe Guo, Steven Van Winckel, Steven Brebels, Quentin Herr, Anna Herr, Manu Perumkunnil. 1-7 [doi]
• Poros: One-Level Architecture-Mapping Co-Exploration for Tensor AlgorithmsFuyu Wang, Minghua Shen. 1-7 [doi]
• Solving the Cold-Start Problem for the Edge: Clustering and Adaptive Deep Learning for Emotion DetectionJunjiao Sun, Laura Gutiérrez-Martín, Celia López-Ongil, José Miranda, Jorge Portilla, Andrés Otero. 1-7 [doi]
• Late Breaking Results: Dynamically Scalable Pruning for Transformer-Based Large Language ModelsJunyoung Lee, Shinhyoung Jang, Seohyun Kim, Jongho Park, Ilhong Suh, Hoon Sung Chwa, Yeseong Kim. 1-2 [doi]
• HFL: Hardware Fuzzing Loop with Reinforcement LearningLichao Wu, Mohamadreza Rostami, Huimin Li 0004, Ahmad-Reza Sadeghi. 1-7 [doi]
• Late Breaking Results: Leveraging Approximate Computing for Carbon-Aware DNN AcceleratorsAikaterini Maria Panteleaki, Konstantinos Balaskas, Georgios Zervakis 0001, Hussam Amrouch, Iraklis Anagnostopoulos. 1-2 [doi]
• GRAMC: General-Purpose and Reconfigurable Analog Matrix Computing ArchitectureLunshuai Pan, Shiqing Wang, Pushen Zuo, Zhong Sun. 1-2 [doi]
• Analog Circuit Anti-Piracy Security by Exploiting Device RatingsHazem H. Hammam, Hassan Aboushady, Haralampos-G. Stratigopoulos. 1-7 [doi]
• Dataflow Optimized Reconfigurable Acceleration for FEM-Based CFD SimulationsAnastassis Kapetanakis, Aggelos Ferikoglou, George Anagnostopoulos, Sotirios Xydis. 1-6 [doi]
• Autonomous UAV-Assisted IoT Systems with Deep Reinforcement Learning Based Data FerryMason Conkel, Wen Zhang, Mimi Xie, Yufang Jin, Chen Pan. 1-7 [doi]
• AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long VectorsNavaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer 0001, Luca Benini. 1-7 [doi]
• A Hardware-Assisted Approach for Non-Invasive and Fine-Grained Memory Power Management in MCUsMichael Kuhn, Patrick Schmid, Oliver Bringmann 0001. 1-7 [doi]
• Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 ProjectCristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Stefania Perri, Fanny Spagnolo, Pasquale Corsonello, Sebastiano Fabio Schifano, Cristian Zambelli, Angelo Garofalo, Francesco Conti 0001, Luca Benini. 1-7 [doi]
• Power- and Deadline-Aware Dynamic Inference on Intermittent Computing SystemsHengrui Zhao, Lei Xun, Jagmohan Chauhan, Geoff V. Merrett. 1-7 [doi]
• TaiChi: Efficient Execution for Multi-DNNs Using Graph-Based SchedulingXilang Zhou, Haodong Lu, Tianchen Wang, Zhuoheng Wan, Jianli Chen, Jun Yu, Kun Wang. 1-7 [doi]
• C3CIM: Constant Column Current Memristor-Based Computation-in-Memory Micro-ArchitectureYashvardhan Biyani, Rajendra Bishnoi, Theofilos Spyrou, Said Hamdioui. 1-7 [doi]
• Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAsPrabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoyang Fan, Bin Qi, Jeff Chen, R. D. Shawn Blanton, John Paul Shen. 1-7 [doi]
• SMT-Based Repairing Real-Time Task SpecificationsAnand Yeolekar, Ravindra Metta, Samarjit Chakraborty. 1-7 [doi]
• SSMDVFS: Microsecond-Scale DVFS on GPGPUs with Supervised and Self-Calibrated MLMinqing Sun, Ruiqi Sun, Yingtao Shen, Wei Yan, Qinfen Hao, An Zou. 1-7 [doi]
• A Resource-Aware Residual-Based Gaussian Belief Propagation Accelerator ToolflowOmar Sharif, Christos-Savvas Bouganis. 1-7 [doi]
• High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual PlatformsNils Bosbach, Rebecca Pelke, Niko Zurstraßen, Jan Henrik Weinstock, Lukas Jünger 0001, Rainer Leupers. 1-7 [doi]
• Multi-Partner Project: Resilient Time-Sensitive Networks (ResTSN)Marc Boyer, Rafik Henia. 1-4 [doi]
• OpenMFDA: Microfluidic Design Automation in Three DimensionsAshton Snelgrove, Daniel Wakeham, Skylar Stockham, Scott Temple, Pierre-Emmanuel Gaillardon. 1-7 [doi]
• Towards Coherent Semantics: A Quantitatively Typed EDSL for Synchronous System DesignRui Chen, Ingo Sander. 1-2 [doi]
• Early Functional Safety and PPA Evaluation of Digital DesignsMichelangelo Bartolomucci, David Kingston, Teo Cupaiuolo, Alessandra Nardi, Riccardo Cantoro. 1-2 [doi]
• Operation Dependency Graph-Based Scheduling for High-Level SynthesisAoxiang Qin, Minghua Shen, Nong Xiao 0001. 1-7 [doi]
• Less is More: Optimizing Function Calling for LLM Execution on Edge DevicesVaratheepan Paramanayakam, Andreas Karatzas, Iraklis Anagnostopoulos, Dimitrios Stamoulis. 1-7 [doi]
• BEAM: A Multi-Channel Optical Interconnect for Multi-GPU SystemsChongyi Yang, Bohan Hu, Peiyu Chen, Yinyi Liu, Wei Zhang, Jiang Xu. 1-7 [doi]
• SegTransformer: Enhancing Softmax Performance Through Segmentation with a ReRAM-Based PIM AcceleratorYu-Chen Wang, Ing-Chao Lin, Yuan-Hao Chang 0001. 1-2 [doi]
• ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact SynthesisHongyang Pan, Keren Zhu 0001, Fan Yang 0001, Zhufei Chu, Xuan Zeng 0001. 1-7 [doi]
• FPGA-Based Acceleration of MCMC Algorithm through Self-Shrinking for Big DataShuanglong Liu, Shiyu Peng, Wan Shen. 1-7 [doi]
• SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit SynthesisKunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu 0010, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang 0033, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui. 1-7 [doi]
• On the Impact of Warpage on BEOL Geometry and Path Delays in Fan-out Wafer-Level PackagingDhruv Thapar, Arjun Chaudhuri, Christopher Bailey, Ravi Mahajan, Krishnendu Chakrabarty. 1-2 [doi]
• 2: An Open-Source End-to-End Hardware Compiler Development Framework for Digital Compute-in-Memory MacroTianchu Dong, Shaoxuan Li, Yihang Zuo, Hongwu Jiang, Yuzhe Ma, Shanshi Huang. 1-2 [doi]
• Efficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern RecognitionMu Nie, Shidong Zhu, Aibin Yan, Cheng Zhuo, Xiaoqing Wen, Tianming Ni. 1-6 [doi]
• Swift-Sim: A Modular and Hybrid GPU Architecture Simulation FrameworkXiangrong Xu, Yuanqiu Lv, Liang Wang, Limin Xiao, Meng Han, Runnan Shen, Jinquan Wang. 1-7 [doi]
• OPS: Outlier-Aware Precision-Slice Framework for LLM AccelerationFangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, Qi Sun, Li Jiang 0002. 1-2 [doi]
• CoupledCB: Eliminating Wasted Pages in Copyback-based Garbage Collection for SSDsJun Li 0062, Xiaofei Xu, Zhibing Sha, Xiaobai Chen, Jieming Yin, Jianwei Liao 0001. 1-7 [doi]
• Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time EvaluationM. Dhilipkumar, Priyanka Bagade, Debapriya Basu Roy. 1-7 [doi]
• TARN: Trust Aware Routing to Enhance Security in 3D Network-on-ChipsHasin Ishraq Reefat, Alec Aversa, Ioannis Savidis, Naghmeh Karimi. 1-7 [doi]
• EGIS: Entropy Guided Image Synthesis for Dataset-Agnostic Testing of RRAM-Based DNNsAnurup Saha, Chandramouli N. Amarnath, Kwondo Ma, Abhijit Chatterjee. 1-7 [doi]
• 2 6T SRAM-Based Digital Compute-in-Memory Macro Featuring a Novel 2T MultiplierPriyanshu Tyagi, Sparsh Mittal. 1-7 [doi]
• FUSIS: Fusing Surrogate Models and Importance Sampling for Efficient Yield EstimationYanfang Liu, Wei W. Xing. 1-7 [doi]
• Late Breaking Results: Practical Electromagnetic Fault Injection on Intel Neural Compute Stick 2Shivam Bhasin, Dirmanto Jap, Prasanna Ravi, Marina Krcek, Stjepan Picek. 1-2 [doi]
• Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum ComputingXiaorang Guo, Jonas Winklmann, Dirk Stober, Amr Elsharkawy, Martin Schulz 0001. 1-6 [doi]
• Time-Domain 3D Electromagnetic Fields Estimation Based on Physics-Informed Deep Learning FrameworkHuifan Zhang, Yun Hu, Pingqiang Zhou. 1-7 [doi]
• Multi-Partner Project: Enabling Digital Technologies for Holistic Health-Lifestyle Motivational and Assisted Supervision Supported by Artificial Intelligence Network (H2TRAIN)Juan A. Montiel-Nelson, Marco Ottella, Paolo Azzoni. 1-7 [doi]
• A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash MemoryRuibin Zhou, Jian Huang, Xianping Liu, Yuhan Wang, Xinrui Zhang, Yungen Peng, Zhiyi Yu. 1-7 [doi]
• MPFS: A Scalable User-Space Persistent Memory File System for Multiple ProcessesBo Ding, Wei Tong 0001, Yu Hua 0001, Yuchong Hu, Dong Huang, Qiankun Liu, Zhangyu Chen, Xueliang Wei, Dan Feng 0001. 1-7 [doi]
• Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing UnitsHong Pang, Carmine Cappetta, Riccardo Massa, Athanasios Vasilopoulos, Elena Ferro, Gamze Islamoglu, Angelo Garofalo, Francesco Conti 0001, Luca Benini, Irem Boybat, Thomas Boesch. 1-7 [doi]
• Multi-Partner Project: A Deep Learning Platform Targeting Embedded Hardware for Edge-AI Applications (NEUROKIT2E)Rajendra Bishnoi, Mohammad Amin Yaldagard, Said Hamdioui, Kanishkan Vadivel, Manolis Sifalakis, Nicolas Daniel Rodriguez, Pedro Julián, Lothar Ratschbacher, Maen Mallah, Yogesh Ramesh Patil, Rashid Ali, Fabian Chersi. 1-7 [doi]
• BIMAX: A Bitwise In-Memory Accelerator Using 6T-SRAM StructureNezam Rohbani, Mohammad Arman Soleimani, Behzad Salami 0001, Osman S. Unsal, Adrián Cristal Kestelman, Hamid Sarbazi-Azad. 1-7 [doi]
• Improving Chip Design Enablement for Universities in Europe - A Position PaperLukas Krupp, Ian O'Connor, Luca Benini, Christoph Studer, Joachim Rodrigues, Norbert Wehn. 1-7 [doi]
• AttentionLib: A Scalable Optimization Framework for Automated Attention Acceleration on FPGAZhenyu Liu, Xilang Zhou, Faxian Sun, Jianli Chen, Jun Yu, Kun Wang. 1-7 [doi]
• Late Breaking Results: SoC-FPGA HW Trojan Leaking Data through EM Covert ChannelMarie-Aïnhoa Nicolas, Jordane Lorandel, Christophe Moy. 1-2 [doi]
• Multi-Partner Project: Securing Future Edge-AI Processors in Practice (CONVOLVE)Sven Argo, Henk Corporaal, Alejandro Garza, Marc Geilen, Manil Dev Gomony, Tim Güneysu, Adrian Marotzke, Fouwad Jamil Mir, Jan Richter-Brockmann, Jeffrey Smith, Mottaqiallah Taouil, Said Hamdioui. 1-7 [doi]
• SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate ExponentiationAndrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti 0001. 1-2 [doi]
• Exploiting SysML v2 Modeling for Automatic Smart Factories ConfigurationMario Libro, Sebastiano Gaiardelli, Marco Panato, Stefano Spellini, Michele Lora, Franco Fummi. 1-7 [doi]
• Empowering Quantum Error Traceability with MoE for Automatic CalibrationTingting Li 0004, Ziming Zhao 0008, Liqiang Lu, Siwei Tan, Jianwei Yin. 1-7 [doi]
• RemapCom: Optimizing Compaction Performance of LSM Trees via Data Block Remapping in SSDsYi Fan, Yajuan Du, Sam H. Noh. 1-7 [doi]
• Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference AcceleratorsFilip Masar, Vojtech Mrazek, Lukás Sekanina. 1-2 [doi]
• Multi-Partner Project: Electric Vehicle Data Acquisition and Valorisation: A Perspective from the OPEVA ProjectAlper Kanak, Salih Ergün, Ibrahim Arif, Ali Serdar Atalay, Serhat Ege Inanç, Oguzhan Herkiloglu, Ahmet Yazici, Yunus Sabri Kirca, Muhammed Ozberk, Alim Kerem Erdogmus, Ali Kafali, Dilara Bayar, Muhammed Oguz Tas, Luca Davoli, Laura Belli, Gianluigi Ferrari 0001, Badar Muneer, Valentina Palazzi, Luca Roselli, Fabio Gelati. 1-7 [doi]
• Efficient Approximate Logic Synthesis with Dual-Phase Iterative FrameworkRuicheng Dai, Xuan Wang, Wenhui Liang, Xiaolong Shen, Menghui Xu, Leibin Ni, Gezi Li, Weikang Qian. 1-7 [doi]
• DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for on-Chip Deployment of Large-Scale DNNsTianyi Yu, Zhonghao Chen, Yiming Chen, Shuang Wang, Yongpan Liu, Huazhong Yang, Xueqing Li. 1-6 [doi]
• RTHeter: Simulating Real-Time Scheduling of Multiple Tasks on Heterogeneous ArchitecturesYinchen Ni, Jiace Zhu, Yier Jin, An Zou. 1-7 [doi]
• Human-Centered Digital Twin for Industry 5.0Francesco Biondani, Luigi Capogrosso, Nicola Dall'Ora, Enrico Fraccaroli, Marco Cristani, Franco Fummi. 1-2 [doi]
• Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based Test GenerationTianyao Lu, Anlin Liu, Bingjie Xia, Peng Liu. 1-7 [doi]
• -1: Understanding and Enabling Physically-Robust Photonic Inverse Design with Adaptive Variation-Aware Subspace OptimizationPingchuan Ma 0012, Zhengqi Gao, Amir Begovic, Meng Zhang, Haoyu Yang, Haoxing Ren, Z. Rena Huang, Duane S. Boning, Jiaqi Gu 0002. 1-7 [doi]
• Hardware-Assisted Ransomware Detection Using Automated Machine LearningZhixin Pan, Ziyu Shu. 1-7 [doi]
• Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement LearningEnrico Russo 0002, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania. 1-7 [doi]
• Cute-Lock: Behavioral and Structural Multi-Key Logic Locking Using Time Base KeysKevin Lopez, Amin Rezaei 0001. 1-7 [doi]
• Improving LLM-Based Verilog Code Generation with Data Augmentation and RLKyungjun Min, SeongHyeon Park, Hyeonwoo Park, Jinoh Cho, Seokhyeong Kang. 1-7 [doi]
• GTN-Cell: Efficient Standard Cell Characterization Using Graph Transformer NetworkLihao Liu, Yunhui Li, Beisi Lu, Li Shang, Fan Yang. 1-7 [doi]
• Co-UP: Comprehensive Core and Uncore Power Management for Latency-Critical WorkloadsKi-Dong Kang, Gyeongseo Park, Daehoon Kim. 1-7 [doi]
• Simultaneous Denoising and Compression for DVS with Partitioned Cache-Like Spatiotemporal FilterQinghang Zhao, Yixi Ji, Jiaqi Wang, Jinjian Wu, Guangming Shi. 1-7 [doi]
• DAOP: Data-Aware Offloading and Predictive Pre-Calculation for Efficient MoE InferenceYujie Zhang, Shivam Aggarwal, Tulika Mitra. 1-7 [doi]
• Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup TablesSubhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar. 1-7 [doi]
• Timing-Driven Detailed Placement with Unsupervised Graph LearningDhoui Lim, Heechun Park. 1-7 [doi]
• PICELF: An Automatic Electronic Layer Layout Generation Framework for Photonic Integrated CircuitsXiaohan Jiang, Yinyi Liu, Peiyu Chen, Wei Zhang, Jiang Xu. 1-7 [doi]
• ReBERT: LLM for Gate-Level to Word-Level Reverse EngineeringLizi Zhang, Azadeh Davoodi, Rasit Onur Topaloglu. 1-7 [doi]
• FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMsXilong Xie, Liang Wang, Limin Xiao, Meng Han, Lin Sun, Shuai Zheng, Xiangrong Xu. 1-7 [doi]
• HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN OptimizationShambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone. 1-7 [doi]
• Bias by Design: Diversity Quantification to Mitigate Structural Bias Effects in AIG Logic OptimizationIsabella Venancia Gardner, Marcel Walter, Yukio Miyasaka, Robert Wille, Michael Cochez. 1-7 [doi]
• SmartMap: Architecture-Agnostic CGRA Mapping Using Graph Traversal and Reinforcement LearningFabio T. Ramos 0001, Pedro E. F. Realino, Wagner A. Junior, Alex Borges Vieira, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif. 1-7 [doi]
• Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop DetectionXizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang 0001. 1-7 [doi]
• PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGAKuangjie Zou, Yifan Zhang, Zicheng Zhang, Guoyu Li, Jianli Chen, Kun Wang, Jun Yu. 1-7 [doi]
• Exploring Large Integer Multiplication for Cryptography Targeting In-Memory ComputingFlorian Krieger, Florian Hirner, Sujoy Sinha Roy. 1-7 [doi]
• Monomorphism-Based CGRA Mapping Via Space and Time DecouplingCristian Tirelli, Rodrigo Otoni, Laura Pozzi 0001. 1-7 [doi]
• Word-Level Counterexample Reduction Methods for Hardware VerificationZhiyuan Yan 0003, Hongce Zhang. 1-7 [doi]
• NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized OverheadAibin Yan, Wangjin Jiang, Han Bao, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. 1-2 [doi]
• SoftmAP: Software-Hardware Co-Design for Integer-Only Softmax on Associative ProcessorsMariam Rakka, Jinhao Li 0006, Guohao Dai, Ahmed M. Eltawil, Mohammed E. Fouda, Fadi J. Kurdahi. 1-7 [doi]
• Assessing Soft Error Reliability in Vectorized Kernels: Vulnerability and Performance Trade-Offs on Arm and RISC-V ISAsGeancarlo Abich. 1-2 [doi]
• Formally Verifying Analog Neural Networks with Device Mismatch VariationsYasmine Abu Haeyeh, Thomas Bartelsmeier, Tobias Ladner, Matthias Althoff, Lars Hedrich, Markus Olbrich. 1-7 [doi]
• Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RLJai-Ming Lin, Zong-Ze Lee, Nan-Chu Lin. 1-7 [doi]
• Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cellsMunhyeon Kim, Yulhwa Kim, Jae-Joon Kim. 1-7 [doi]
• EDA-Aware RTL Generation with Large Language ModelsMubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace. 1-6 [doi]
• SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision SupportHaikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang 0001, Xiyuan Tang. 1-7 [doi]
• Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTANFatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnór Kristmundsson, Alexander Schober, Téo Bernier, Matti Käyrä, Ulf Schlichtmann, Rocco Jonack. 1-6 [doi]
• Towards Robust RRAM-Based Vision Transformer Models with Noise-Aware Knowledge DistillationWenyong Zhou, Zhengwu Liu, Taiqiang Wu, Chenchen Ding, Yuan Ren, Ngai Wong. 1-2 [doi]
• Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA SemanticsSören Tempel, Tobias Brandt, Christoph Lüth, Christian Dietrich, Rolf Drechsler. 1-7 [doi]
• Energy-Aware Error Correction Method for Indoor Positioning and TrackingDonguk Kim, Donkyu Baek, Yukai Chen, Enrico Macii, Massimo Poncino. 1-2 [doi]
• TxISC: Transactional File Processing in Computational SSDsPenghao Sun, Shengan Zheng, Kaijiang Deng, Guifeng Wang, Jin Pu, Jie Yang, Maojun Yuan, Feng Zhu 0024, Shu Li, Linpeng Huang. 1-7 [doi]
• Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTMJiayu Yang, Luyi Guo, Yicheng Li, Wang Wang, Zixu Li, Manni Li, Zijian Huang, Yinyin Lin, Yun Yin, Hongtao Xu. 1-7 [doi]
• ${MC}^{3}$: Memory Contention-Based Covert Channel Communication on Shared DRAM System-on-ChipsIsmet Dagli, James Crea, Soner Seçkiner, Yuanchao Xu 0001, Selçuk Köse, Mehmet E. Belviranli. 1-7 [doi]
• ConZone: A Zoned Flash Storage Emulator for Consumer DevicesDingcui Yu, Jialin Liu, Yumiao Zhao, Wentong Li 0002, Ziang Huang, Zonghuan Yan, Mengyang Ma, Liang Shi 0001. 1-7 [doi]
• SimGen: Simulation Pattern Generation for Efficient Equivalence CheckingCarmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic. 1-7 [doi]
• Write-Optimized Persistent Hash Index for Non-Volatile MemoryRenzhi Xiao, Dan Feng 0001, Yuchong Hu, Yucheng Zhang, Lanlan Cui, Lin Wang. 1-7 [doi]
• HyAtten: Hybrid Photonic-Digital Architecture for Accelerating Attention MechanismHuize Li, Dan Chen 0006, Tulika Mitra. 1-7 [doi]
• REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based AttacksHassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jörg Henkel, Kuan-Hsun Chen. 1-2 [doi]
• CPP-SGS: Cycle-Accurate Power Prediction Framework via SNN and Genetic Signal SelectionTong Liu, Zijun Jiang, Yangdi Lyu. 1-2 [doi]
• One More Motivation to Use Evaluation Tools This Time for Hardware Multiplicative Masking of AESHemin Rahimi, Amir Moradi 0001. 1-7 [doi]
• Online Learning for Dynamic Structural Characterization in Electron Energy Loss SpectroscopyM. Lakshmi Varshika, Jonathan Hollenbach, Nicolas Bohm Agostini, Ankur Limaye, Antonino Tumeo, Anup Das 0001. 1-7 [doi]
• Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project PerspectiveFrancesca Palumbo, Francesco Ratto, Claudio Rubattu, Maria Katiuscia Zedda, Tiziana Fanni, Veena Rao, Bart Driessen, Jerónimo Castrillón. 1-7 [doi]
• Teleoperation as a Step Towards Fully Autonomous SystemsAlex Bendrick, Daniel Tappe, Nora Sperling, Rolf Ernst, Andrea Nota, Selma Saidi, Frank Diermeyer. 1-8 [doi]
• Timing-Driven Global Placement With Hybrid Heuristics and Nadam-Based Net WeightingLinhao Lu, Wenxin Yu 0001, Hongwei Tian, Chengjin Li, Xinmiao Li, Zhaoqi Fu, Zhengjie Zhao, Jingwei Lu. 1-7 [doi]
• Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven ArchitectureIlkin Aliyev, Jesus Lopez, Tosiron Adegbija. 1-7 [doi]
• HyMM: A Hybrid Sparse-Dense Matrix Multiplication Accelerator for GCNsHunjong Lee, Jihun Lee, Jaewon Seo, Yunho Oh, Myung Kuk Yoon, Gunjae Koo. 1-7 [doi]
• DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Partitioning, Low-Degree Sparsity, and Asynchronous Sub-BatchZhen Yu, Jinhao Li 0006, Jiaming Xu, Shan Huang, Jiancai Ye, Ningyi Xu, Guohao Dai. 1-7 [doi]
• WinAcc: Window-based Acceleration of Neural Networks Using Block Floating PointXin Ju 0005, Jun He, Mei Wen, Jing Feng, Yasong Cao, Junzhong Shen, Zhaoyun Chen, Yang Shi. 1-7 [doi]
• Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGAJindong Li 0001, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang 0080, Yi Zeng 0001. 1-7 [doi]
• Fast Interpreter-Based Instruction Set Simulation for Virtual PrototypesManfred Schlägl, Daniel Große. 1-7 [doi]
• SPB: Towards Low-Latency CXL Memory via Speculative Protocol BypassingJunbum Park, Yongho Lee, Sungbin Jang, Wonyoung Lee 0001, Seokin Hong. 1-7 [doi]
• Comb Frequency Division Multiplexing: A Non-Binary Modulation for AirGap Covert Channel TransmissionMohamed Alla Eddine Bahi, Maria Mendez Real, Maxime Pelcat. 1-2 [doi]
• ML-Based AIG Timing Prediction to Enhance Logic OptimizationWenjing Jiang, Jin Yan, Sachin S. Sapatnekar. 1-2 [doi]
• FAMERS: An FPGA Accelerator for Memory-Efficient Edge-Rendered 3D Gaussian SplattingYuanfang Wang, Yu Li, Jianli Chen, Jun Yu, Kun Wang. 1-7 [doi]
• Cybersecurity Challenges of Autonomous SystemsMohammad Hamad, Christian Prehofer, Mikael Asplund, Tobias Löhr, Lucas Bublitz, Alexander Zeh, Mridula Singh, Sebastian Steinhorst. 1-10 [doi]
• Joint DNN Partition and Thread Allocation Optimization for Energy-Harvesting MEC SystemsYizhou Shi, Liying Li 0002, Yue Zeng, Peijin Cong, Junlong Zhou. 1-7 [doi]
• Genetic Algorithm-Driven IMC Mapping for CNNs Using Mixed Quantization and MLC FeFETsAlptekin Vardar, Franz Müller 0001, Gonzalo Cuñarro, Nellie Laleni, Nandakishor Yadav, Thomas Kämpfe. 1-7 [doi]
• A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional NetworksYingnan Zhao 0001, Ke Wang 0030, Ahmed Louri. 1-7 [doi]
• Gradient Approximation of Approximate Multipliers for High-Accuracy Deep Neural Network RetrainingChang Meng, Wayne P. Burleson, Weikang Qian, Giovanni De Micheli. 1-7 [doi]
• Rhychee-FL: Robust and Efficient Hyperdimensional Federated Learning with Homomorphic EncryptionYujin Nam, Abhishek Moitra, Yeshwanth Venkatesha, Xiaofan Yu 0001, Gabrielle De Micheli, Xuan Wang, Minxuan Zhou, Augusto Vega, Priyadarshini Panda, Tajana Rosing. 1-7 [doi]
• LCache: Log-Structured SSD Caching for Training Deep Learning ModelsShucheng Wang, Zhiguo Xu, Zhandong Guo, Jian-Sheng, Kaiye Zhou, Qiang Cao 0001. 1-7 [doi]
• REACT: Randomized Encryption with AI-Controlled Targeting for Next-Gen Secure CommunicationZhangying He, Hossein Sayadi. 1-2 [doi]
• A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided SignalsHaoran Lu, Xun Jiang 0002, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang 0001. 1-7 [doi]
• Efficient Approximate Nearest Neighbor Search via Data-Adaptive Parameter Adjustment in Hierarchical Navigable Small GraphsHuijun Jin, Jieun Lee 0006, Shengmin Piao, Sangmin Seo 0001, Sein Kwon, Sanghyun Park 0003. 1-7 [doi]
• Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord InjuriesAdrian Evans, Victor Roux-Sibillon, Joe Saad, Ivan Miro Panades, Tetiana Aksenova, Lorena Anghel. 1-2 [doi]
• Designing Resilient Autonomous Systems with the Reflex PatternJulian Demicoli, Sebastian Steinhorst. 1-7 [doi]
• Design, Implementation and Validation of NSCP: A New Secure Channel Protocol for Hardened IoTJoan Bushi, Alberto Battistello, Guido Bertoni, Vittorio Zaccaria. 1-7 [doi]
• FrEDDY: Modular and Efficient Framework to Engineer Decision Diagrams YourselfRune Krauss, Jan Zielasko, Rolf Drechsler. 1-2 [doi]
• Odin: Learning to Optimize Operation Unit Configuration for Energy-efficient DNN InferencingGaurav Narang, Janardhan Rao Doppa, Partha Pratim Pande. 1-7 [doi]
• InterA-ECC: Interconnect-Aware Error Correction in STT-MRAMSurendra Hemaram, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Tommaso Marinelli, Anita Farokhnejad, Gouri Sankar Kar. 1-2 [doi]
• Hardware/Software Runtime for GPSA Protection in RISC-V Embedded CoresLouis Savary, Simon Rokicki, Steven Derrien. 1-7 [doi]
• Minimum Time Maximum Fault Coverage Testing of Spiking Neural NetworksSpyridon Raptis, Haralampos-G. Stratigopoulos. 1-7 [doi]
• Multi-Partner Project: Sports Performance and Health Assessment in the DistriMuse ProjectLuca Davoli, Laura Belli, Veronica Mattioli, Riccardo Raheli, Gianluigi Ferrari 0001, Lorenzo Priano, Jaromir Hubalek, Lukás Smital, Andrea Nemcová, Daniela Chlibkova, Vlastimil Benes, Johan Plomp. 1-7 [doi]
• Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro PlacementHao Gu, Xinglin Zheng, Youwen Wang, Keyu Peng, Ziran Zhu, Jun Yang. 1-7 [doi]
• Efficient SAT-Based Bounded Model Checking of Evolving SystemsSophie Andrews, Matthew Sotoudeh, Clark Barrett. 1-7 [doi]
• Protecting Cyber-Physical Systems via Vendor-Constrained Security Auditing with Reinforcement LearningNan Wang, Kai Li, Lijun Lu, Zhiwei Zhao, Zhiyuan Ma. 1-7 [doi]
• Location is All You Need: Efficient Lithographic Hotspot Detection Using Only Polygon LocationsYujia Wang, Jiaxing Wang, Dan Feng, Yuzhe Ma, Kang Liu. 1-7 [doi]
• Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of ThingsJakub Lojda, Josef Strnadel, Pavel Smrz, Václav Simek. 1-7 [doi]
• Multi-Partner Project: Artificial Intelligence in Manufacturing Leading to Sustainability and the Consideration of Human Aspects (AIMS5.0)Anouar Nechi, Yasin Ghafourian, Belal Abu-Naim, Thomas Gutt, George Dimitrakopoulos 0001, Amira Moualhi, Mladen Berekovic, Pál Varga, Markus Tauber. 1-4 [doi]
• Compact Non-Volatile Lookup Table Architecture Based on Ferroelectric FET Array Through In-Situ Combinatorial One-Hot Encoding for Reconfigurable ComputingWeikai Xu, Meng Li 0004, Qianqian Huang, Ru Huang 0001. 1-7 [doi]
• Integrated Hardware Annealing Based on Langevin Dynamics for Ising MachinesYongchao Liu, Lianlong Sun, Michael C. Huang 0001, Hui Wu 0007. 1-6 [doi]
• RT-VirtIO: Towards the Real-Time Performance of VirtIO in a Two-Tier Computing ArchitectureSiwei Ye, Minqing Sun, Huifeng Zhu, Yier Jin, An Zou. 1-7 [doi]
• Umbra: An Efficient Framework for Trusted Execution on Modern TrustZone-Enabled MicrocontrollersStefano Mercogliano, Alessandro Cilardo. 1-2 [doi]
• Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear ProgrammingDevin Pohl, Aaron R. Young, Kazi Asifuzzaman, Narasinga Rao Miniskar, Jeffrey S. Vetter. 1-7 [doi]
• Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output LogicLang Feng 0001, Rongjian Liang, Hongxin Kong. 1-7 [doi]
• Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage)Mehdi B. Tahoori, Jürgen Becker 0001, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn. 1-6 [doi]
• TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer ParallelismHaomin Li 0002, Fangxin Liu, Zongwu Wang, Dongxu Lyu, Shiyuan Huang, Ning Yang, Qi Sun, Zhuoran Song, Li Jiang 0002. 1-7 [doi]
• LLM-SRAF: Sub-Resolution Assist Feature Generation Using Large Language ModelTianyi Li, Zhexin Tang, Tao Wu, Bei Yu 0001, Jingyi Yu, Hao Geng. 1-7 [doi]
• A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area FootprintHuseyin Ekin Sumbul, Arne Symons, Lita Yang, Huichu Liu, Tony F. Wu, Matheus Trevisan Moreira, Debabrata Mohapatra, Abhinav Agarwal, Kaushik Ravindran, Chris Thompson, Yuecheng Li, Edith Beigné. 1-7 [doi]
• Multi-Partner Project: Safe, Secure and Dependable Multi-UAV Systems for Search and Rescue OperationsPanagiota Nikolaou, Antonis Savva, Ioannis Sorokos, Koorosh Aslansefat, Sondess Missaoui, Mohammed Naveed Akram, Daniel Hillen, Marc Lorenz, Martin D. Walker, Manos Papoutsakis, Simos Gerasimou, Panayiotis Kolios, Yiannis Papadopoulos, Jan Reich, Sotiris Ioannidis, Maria K. Michael. 1-7 [doi]
• Adaptive Multi-Threshold Encoding for Energy-Efficient ECG Classification Architecture Using Spiking Neural NetworkSumit Diware, Yingzhou Dong, Mohammad Amin Yaldagard, Said Hamdioui, Rajendra Bishnoi. 1-7 [doi]
• Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCsCyril Koenig, Enrico Zelioli, Luca Benini. 1-7 [doi]
• TKD: An Efficient Deep Learning Compiler with Cross-Device Knowledge DistillationYiming Ma, Chaoyao Shen, LinFeng Jiang, Tao Xu, Meng Zhang. 1-7 [doi]
• Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUsZhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu 0005, Le Ye, Ru Huang 0001, Tianyu Jia. 1-7 [doi]
• HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICsKlajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf. 1-7 [doi]
• Law as a Design Consideration for Automated Vehicles Suitable to Transport Intoxicated PersonsWilliam H. Widen, Marilyn Claire Wolf. 1-7 [doi]
• Signal Prediction for Digital Circuits by Sigmoidal Approximations Using Neural NetworksJosef Salzmann, Ulrich Schmid 0001. 1-2 [doi]
• OLORAS: Online LOng Range Action Segmentation for Edge DevicesFilippo Ziche, Nicola Bombieri. 1-7 [doi]
• Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar ProcessorsLuca Colagrande, Jayanth Jonnalagadda, Luca Benini. 1-2 [doi]
• Cocktail: Chunk-Adaptive Mixed-Precision Quantization for Long-Context LLM InferenceWei Tao, Bin Zhang, Xiaoyang Qu, Jiguang Wan, Jianzong Wang. 1-7 [doi]
• FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage VariationXiangyu Li, Weichong Chen, Ruida Hong, Jinghai Wang, Ningyuan Yin, Zhiyi Yu. 1-7 [doi]
• Thanos: Energy-Efficient Keyword Spotting Processor with Hybrid Time-Feature-Frequency-Domain Zero-SkippingSangyeon Kim, Hyunmin Kim, Sungju Ryu. 1-7 [doi]
• Polynomial Formal Verification of Sequential Circuits Using Weighted-AIGsMohamed A. Nadeem, Chandan Kumar Jha 0001, Rolf Drechsler. 1-7 [doi]
• Optimal State Preparation for Logical Arrays on Zoned Neutral Atom Quantum ComputersYannick Stade, Ludwig Schmid, Lukas Burgholzer, Robert Wille. 1-7 [doi]
• EILID: Execution Integrity for Low-end IoT DevicesSashidhar Jakkamsetti, Youngil Kim, Andrew Searles, Gene Tsudik. 1-7 [doi]
• A Multi-Stage Potts Machine Based on Coupled CMOS Ring OscillatorsYilmaz Ege Gonul, Baris Taskin. 1-7 [doi]
• Dancer: Dynamic Compression and Quantization Architecture for Deep Graph Convolutional NetworkYunhao Dong, Zhaoyu Zhong, Yi Wang 0003, Chenlin Ma, Tianyu Wang 0009. 1-7 [doi]
• AeroDiffusion: Complex Aerial Image Synthesis with Keypoint-Aware Text Descriptions and Feature-Augmented Diffusion ModelsDouglas J. Townsell, Mimi Xie, Bin Wang, Fathi Amsaad, Varshitha Reddy Thanam, Wen Zhang. 1-7 [doi]
• Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended AbstractNiels Mook, Erwin de Kock, Bas Arts, Soham Chakraborty, Arie van Deursen. 1-2 [doi]
• COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning AcceleratorsJiHoon Park, Jeongin Choe, Dohyun Kim, Jae-Joon Kim. 1-7 [doi]
• Bridging the Gap Between Anomaly Detection and Runtime Verification: H-ClassifiersHagen Heermann, Christoph Grimm 0001. 1-7 [doi]
• An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core SystemsXiaoze Lin, Liyang Lai, Huawei Li, Biwei Xie, Xingquan Li. 1-7 [doi]
• Dcha: Distributed-Centralized Heterogeneous Architecture Enables Efficient Multi-Task Processing for Smart SensingErxiang Ren, Cheng Qu, Li Luo, Yonghua Li, Zheyu Liu, Xinghua Yang, Qi Wei, Fei Qiao. 1-7 [doi]
• A Novel Frequency-Spatial Domain Aware Network for Fast Thermal Prediction in 2.5D ICsDekang Zhang, Dan Niu, Zhou Jin 0001, Yichao Dong, Jingweijia Tan, Changyin Sun. 1-7 [doi]
• Accelerating Cell-Aware Model Generation for Sequential Cells using Graph TheoryGianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard 0001, Arnaud Virazel. 1-7 [doi]
• DE2: SAT-Based Sequential Logic Decryption with a Functional DescriptionYou Li, Guannan Zhao, Yunqi He, Hai Zhou 0001. 1-7 [doi]
• Enabling Security on the Edge: A CHERI Compartmentalized Network StackDonato Ferraro, Andrea Bastoni, Alexander Zuepke, Andrea Marongiu. 1-7 [doi]
• UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHEYuying Zhang, Sharad Sinha, Jiang Xu, Wei Zhang. 1-7 [doi]
• PFP: Parallel Floating-Point Vector Multiplication Acceleration in MAGIC ReRAMWenqing Wang, Ziming Chen, Quan Deng, Liang Fang. 1-7 [doi]
• NVCiM-PT: An NVCiM-Assisted Prompt Tuning Framework for Edge LLMsRuiyang Qin, Pengyu Ren, Zheyu Yan, Liu Liu, Dancheng Liu, Amir Nassereldine, Jinjun Xiong, Kai Ni 0004, X. Sharon Hu, Yiyu Shi 0001. 1-7 [doi]
• Leveraging Hot Data in a Multi-Tenant Accelerator for Effective Shared Memory ManagementChunmyung Park, Jicheon Kim, Eunjae Hyun, Xuan Truong Nguyen, Hyuk-Jae Lee. 1-7 [doi]
• ChipVQA: Benchmarking Visual Language Models for Chip DesignHaoyu Yang, Qijing Huang, Nathaniel Ross Pinckney, Walker J. Turner, Wenfei Zhou, Yanqing Zhang 0002, Chia-Tung Ho, Chen-Chia Chang, Haoxing Ren. 1-6 [doi]
• A Parallel Floating Random Walk Solver for Reproducible and Reliable Capacitance ExtractionJiechen Huang, Shuailong Liu, Wenjian Yu. 1-7 [doi]
• A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET ProcessPrashanth Mohan, Siddharth Das, Oguz Atli, Josh Joffrion, Ken Mai. 1-6 [doi]
• Pasta on Edge: Cryptoprocessor for Hybrid Homomorphic EncryptionAikata Aikata, Daniel Sanz Sobrino, Sujoy Sinha Roy. 1-7 [doi]
• SparseInfer: Training-free Prediction of Activation Sparsity for Fast LLM InferenceJiho Shin, Hoeseok Yang, Youngmin Yi. 1-7 [doi]
• LightMamba: Efficient Mamba Acceleration on FPGA with Quantization and Hardware Co-designRenjie Wei, Songqiang Xu, Linfeng Zhong, Zebin Yang, Qingyu Guo, Yuan Wang, Runsheng Wang, Meng Li. 1-7 [doi]
• A Two-level SLC Cache Hierarchy for Hybrid SSDsLi Cai, Zhibing Sha, Jun Li 0062, Jiaojiao Wu, Huanhuan Tian, Zhigang Cai, Jianwei Liao 0001. 1-7 [doi]
• An Efficient On-Chip Reference Search and Optimization Algorithms for Variation-Tolerant STT-MRAM ReadKiho Chung, Youjin Choi, Donguk Seo, Yoonmyung Lee. 1-7 [doi]
• Neural Circuit Parameter Prediction for Efficient Quantum Data LoadingDohun Kim, Sunghye Park, Seokhyeong Kang. 1-6 [doi]
• CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCsDimosthenis Georgoulas, Yiorgos Tsiatouhas, Vasileios Tenentes. 1-7 [doi]
• AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel MergingEnhao Tang, Shun Li, Hao Zhou, Guohao Dai, Jun Lin, Kun Wang. 1-7 [doi]
• Buddy ECC: Making Cache Mostly Clean in CXL-Based Memory Systems for Enhanced Error Correction at Low CostYongho Lee, Junbum Park, Osang Kwon, Sungbin Jang, Seokin Hong. 1-7 [doi]
• Xray: Detecting and Exploiting Vulnerabilities in Arm AXI InterconnectsMelisande Zonta-Roudes, Nora Hinderling, Shweta Shinde. 1-7 [doi]
• HyperDyn: Dynamic Dimensional Masking for Efficient Hyper-Dimensional ComputingFangxin Liu, Haomin Li 0002, Zongwu Wang, Dongxu Lyu, Li Jiang 0002. 1-7 [doi]
• DuSGAI: A Dual-Side Sparse GEMM Accelerator with Flexible InterconnectsWujie Zhong, Yangdi Lyu. 1-2 [doi]
• iRw: An Intelligent RewritingHaisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, Bei Yu 0001. 1-2 [doi]
• Late Breaking Results: A Data Compaction Strategy for Extensive Test Flows of Memories Embedded in Automotive SoCsPaolo Bernardi, B. Borio, Giorgio Insinga, B. Mendicino, M. Battilana, M. Coppetta, N. Mautone, Pierre Scaramuzza, F. Tengler, Rudolf Ullmann. 1-2 [doi]
• RankMap: Priority-Aware Multi-DNN Manager for Heterogeneous Embedded DevicesAndreas Karatzas, Dimitrios Stamoulis, Iraklis Anagnostopoulos. 1-7 [doi]
• Quantifying Trade-Offs in Power, Performance, Area, and Total Carbon Footprint of Future Three-Dimensional Integrated Computing SystemsDanielle Grey-Stewart, David Kong, Mariam Elgamal, Georgios Kyriazidis, Jalil Morris, Gage Hills. 1-7 [doi]
• FlexENM: A Flexible Encrypting-Near-Memory with Refresh-Less eDRAM-Based Multi-Mode AESHyunseob Shin, Jaeha Kung. 1-7 [doi]
• Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal AttentionBangqi Fu, Lixin Liu, Qijing Wang, Yutao Wang, Martin D. F. Wong, Evangeline F. Y. Young. 1-7 [doi]
• An Effective and Efficient Cross-Link Insertion for Non-Tree Clock Network SynthesisJinghao Ding, Jiazhi Wen, Hao Tang, Zhaoqi Fu, Mengshi Gong, Yuanrui Qi, Wenxin Yu 0001, Jinjia Zhou. 1-7 [doi]