Abstract is missing.
- Full-stack quantum computing systems in the NISQ era: algorithm-driven and hardware-aware compilation techniquesMedina Bandic, Sebastian Feld, Carmen G. Almudéver. 1-6 [doi]
- XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical SystemsLeonard Masing, Tobias Dörr, Florian Schade, Jürgen Becker 0001, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios Kelefouras, Konstantinos Antonopoulos, Nikos S. Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm 0005, Geza Nemeth, Fahad Siddiqui 0001, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales. 1-5 [doi]
- tweedledum: A Compiler Companion for Quantum ComputingBruno Schmitt, Giovanni De Micheli. 7-12 [doi]
- A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA EmulationKevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman. 13-16 [doi]
- Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic CircuitsAlexander J. Edwards, Naimul Hassan, Dhritiman Bhattacharya, Mustafa M. Shihab, Peng Zhou, Xuan Hu, Jayasimha Atulasimha, Yiorgos Makris, Joseph S. Friedman. 17-22 [doi]
- Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal ApproachMichael Raitza, Steffen Märcker, Shubham Rai, Akash Kumar 0001. 23-28 [doi]
- Design enablement of CFET devices for sub-2nm CMOS nodesOdysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert. 29-33 [doi]
- Majority-based Design Flow for AQFP Superconducting FamilyGiulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli. 34-39 [doi]
- A Software Architecture to Control Service-Oriented Manufacturing SystemsSebastiano Gaiardelli, Stefano Spellini, Marco Panato, Michele Lora, Franco Fummi. 40-43 [doi]
- Comprehensive and Accessible Channel Routing for Microfluidic DevicesGerold Fink, Philipp Ebner, Robert Wille. 44-47 [doi]
- XST: A Crossbar Column-wise Sparse Training for Efficient Continual LearningFan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Cao 0001, Deliang Fan. 48-51 [doi]
- Energy-Efficient Brain-Inspired Hyperdimensional Computing Using Voltage ScalingSizhe Zhang, Ruixuan Wang, Dongning Ma, Jeff Jun Zhang, Xunzhao Yin, Xun Jiao. 52-55 [doi]
- Error Generation for 3D NAND Flash MemoryWeihua Liu, Fei Wu 0005, Songmiao Meng, Xiang Chen, Changsheng Xie. 56-59 [doi]
- Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault InjectionsYangchao Zhang, Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Masanori Hashimoto. 60-63 [doi]
- Exploiting Arbitrary Paths for the Simulation of Quantum Circuits with Decision DiagramsLukas Burgholzer, Alexander Ploier, Robert Wille. 64-67 [doi]
- A Novel Neuromorphic Processors Realization of Spiking Deep Reinforcement Learning for Portfolio ManagementSeyyed Amirhossein Saeidi, Forouzan Fallah, Soroush Barmaki, Hamed Farbeh. 68-71 [doi]
- In-situ Tuning of Printed Neural Networks for Variation ToleranceMichael Hefenbrock, Dennis D. Weller, Jasmin Aghassi-Hagmann, Michael Beigl, Mehdi B. Tahoori. 72-75 [doi]
- Practical identity recognition using WiFi's Channel State InformationCristian Turetta, Florenc Demrozi, Philipp H. Kindt, Alejandro Masrur, Graziano Pravadelli. 76-79 [doi]
- A RDMA Interface for Ultra-Fast Ultrasound Data-Streaming over an Optical LinkAndrea Cossettini, Konstantin Taranov, Christian Vogt 0002, Michele Magno, Torsten Hoefler, Luca Benini. 80-83 [doi]
- Robust Human Activity Recognition Using Generative Adversarial Imputation NetworksDina Hussein, Aaryan Jain, Ganapati Bhat. 84-87 [doi]
- HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive XbarsAdarsh Kosta, Efstathia Soufleri, Indranil Chakraborty, Amogh Agrawal, Aayush Ankit, Kaushik Roy 0001. 88-91 [doi]
- A Resource-efficient Spiking Neural Network Accelerator Supporting Emerging Neural EncodingDaniel Gerlinghoff, Zhehui Wang, Xiaozhe Gu, Rick Siow Mong Goh, Tao Luo. 92-95 [doi]
- Scalable Hardware Acceleration of Non-Maximum SuppressionChunyun Chen, Tianyi Zhang, Zehui Yu, Adithi Raghuraman, Shwetalaxmi Udayan, Jie Lin 0001, Mohamed M. Sabry Aly. 96-99 [doi]
- Active Learning of Abstract System Models from Traces using Model CheckingNatasha Yogananda Jeppu, Tom Melham, Daniel Kroening. 100-103 [doi]
- Reducing the Configuration Overhead of the Distributed Two-level Control SystemYu Yang, Dimitrios Stathis 0001, Ahmed Hemani. 104-107 [doi]
- BatchLens: A Visualization Approach for Analyzing Batch Jobs in Cloud SystemsShaolun Ruan, Yong Wang, Hailong Jiang, Weijia Xu, Qiang Guan. 108-111 [doi]
- FlowAcc: Real-Time High-Accuracy DNN-based Optical Flow Accelerator in FPGAYehua Ling, Yuanxing Yan, Kai Huang 0001, Gang Chen. 112-115 [doi]
- On Exploiting Patterns For Robust FPGA-based Multi-accelerator Edge Computing SystemsSeyyed Ahmad Razavi, Hsin-Yu Ting, Tootiya Giyahchi, Eli Bozorgzadeh. 116-119 [doi]
- RLPlace: Deep RL Guided Heuristics for Detailed Placement OptimizationUday Mallappa, Sreedhar Pratty, David Brown. 120-123 [doi]
- Deadlock Analysis and Prevention for Intersection Management Based on Colored Timed Petri NetsTsung-Lin Tsou, Chung-Wei Lin, Iris Hui-Ru Jiang. 124-127 [doi]
- Attack Data Generation Framework for Autonomous Vehicle SensorsJan Lauinger, Andreas Finkenzeller, Henrik Lautebach, Mohammad Hamad, Sebastian Steinhorst. 128-131 [doi]
- Contract-Based Quality-of-Service Assurance in Dynamic Distributed SystemsLea Schönberger, Susanne Graf, Selma Saidi, Dirk Ziegenbein, Arne Hamann. 132-135 [doi]
- EffiCSense: an Architectural Pathfinding Framework for Energy-Constrained Sensor ApplicationsJonah Van Assche, Ruben Helsen, Georges G. E. Gielen. 136-141 [doi]
- Topology Optimization of Operational Amplifier in Continuous Space via Graph EmbeddingJialin Lu, Liangbo Lei, Fan Yang 0001, Li Shang, Xuan Zeng 0001. 142-147 [doi]
- A Charge Flow Formulation for Guiding Analog/Mixed-Signal PlacementTonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar. 148-153 [doi]
- Are Analytical Techniques Worthwhile for Analog IC Placement?Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. 154-159 [doi]
- Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo TheoriesHao Chen, Walker J. Turner, David Z. Pan, Haoxing Ren. 160-165 [doi]
- Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor ArraysNibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar. 166-171 [doi]
- MUSCAT: MUS-based Circuit Approximation TechniqueLinus Witschen, Tobias Wiersema, Matthias Artmann, Marco Platzner. 172-177 [doi]
- OPACT: Optimization of Approximate Compressor Tree for Approximate MultiplierWeihua Xiao, Cheng Zhuo, Weikang Qian. 178-183 [doi]
- Learning to Design Accurate Deep Learning Accelerators with Inaccurate MultipliersParas Jain 0001, Safeen Huda, Martin Maas 0001, Joseph E. Gonzalez, Ion Stoica, Azalia Mirhoseini. 184-189 [doi]
- Cross-Layer Approximation For Printed Machine Learning CircuitsGiorgos Armeniakos, Georgios Zervakis 0001, Dimitrios Soudris, Mehdi B. Tahoori, Jörg Henkel. 190-195 [doi]
- A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate ComputingBo Liu 0019, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang 0006. 196-201 [doi]
- Towards Energy-Efficient CGRAs via Stochastic ComputingBo Wang, Rong Zhu, Jiaxing Shang, Dajiang Liu. 202-207 [doi]
- DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural NetworksBo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou. 208-213 [doi]
- VW-SDK: Efficient Convolutional Weight Mapping Using Variable Windows for Processing-In-Memory ArchitecturesJohnny Rhe, Sungmin Moon, Jong Hwan Ko. 214-219 [doi]
- A Uniform Latency Model for DNN Accelerators with Diverse Architectures and DataflowsLinyan Mei, Huichu Liu, Tony F. Wu, H. Ekin Sumbul, Marian Verhelst, Edith Beigné. 220-225 [doi]
- MEDEA: A Multi-objective Evolutionary Approach to DNN Hardware MappingEnrico Russo, Maurizio Palesi, Salvatore Monteleone, Davide Patti, Giuseppe Ascia, Vincenzo Catania. 226-231 [doi]
- DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN AcceleratorsSheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna. 232-237 [doi]
- AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic AlgorithmsNael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Höfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jörg Vögel, Nguyen Anh Vu Doan, Maurizio Martina, Jürgen Becker 0001, Walter Stechele. 238-243 [doi]
- AdaFlow: A Framework for Adaptive Dataflow CNN Acceleration on FPGAsGuilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 244-249 [doi]
- Raw Filtering of JSON Data on FPGAsTobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich. 250-255 [doi]
- GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing AcceleratorJinho Lee, Burin Amornpaisannon, Tulika Mitra, Trevor E. Carlson. 256-261 [doi]
- RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register ChainsRong Zhu, Bo Wang, Dajiang Liu. 262-267 [doi]
- PathSeeker: A Fast Mapping Algorithm for CGRAsMahesh Balasubramanian 0001, Aviral Shrivastava. 268-273 [doi]
- Improving Technology Mapping for And-Inverter-ConesMartin Thümmler, Shubham Rai, Akash Kumar 0001. 274-279 [doi]
- Symbiotic Safety: Safe and Efficient Human-Machine Collaboration by utilizing RulesTasuku Ishigooka, Hiroyuki Yamada, Satoshi Otsuka, Nobuyasu Kanekawa, Junya Takahashi. 280-281 [doi]
- A Middleware Journey from Microcontrollers to MicroprocessorsMichael Pöhnl, Alban Tamisier, Tobias Blass. 282-286 [doi]
- Reliable Distributed SystemsPhilipp Mundhenk, Arne Hamann, Andreas Heyl, Dirk Ziegenbein. 287-291 [doi]
- Algorithm-Hardware Co-Design for Efficient Brain-Inspired Hyperdimensional Learning on EdgeYang Ni, Yeseong Kim, Tajana Rosing, Mohsen Imani. 292-297 [doi]
- PoisonHD: Poison Attack on Brain-Inspired Hyperdimensional ComputingRuixuan Wang, Xun Jiao. 298-303 [doi]
- AIME: Watermarking AI Models by Leveraging ErrorsDhwani Mehta, Nurun N. Mondol, Farimah Farahmandi, Mark M. Tehranipoor. 304-309 [doi]
- ThingNet: A Lightweight Real-time Mirai IoT Variants Hunter through CPU Power FingerprintingZhuoran Li, Dan Zhao. 310-315 [doi]
- M2M-Routing: Environmental Adaptive Multi-agent Reinforcement Learning based Multi-hop Routing Policy for Self-Powered IoT SystemsWen Zhang, Jeff Zhang 0001, Mimi Xie, Tao Liu, Wenlu Wang, Chen Pan. 316-321 [doi]
- Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum ComputersAbdullah Ash-Saki, Rasit Onur Topaloglu, Swaroop Ghosh. 322-327 [doi]
- Circuits for Measurement Based Quantum State PreparationNiels Gleinig, Torsten Hoefler. 328-333 [doi]
- OPTIC: A Practical Quantum Binary Classifier for Near-Term Quantum ComputersTirthak Patel, Daniel Silver, Devesh Tiwari. 334-339 [doi]
- Scalable Variational Quantum Circuits for Autoencoder-based Drug DiscoveryJunde Li, Swaroop Ghosh. 340-345 [doi]
- Towards Low-Cost High-Accuracy Stochastic Computing Architecture for Univariate Functions: Design and Design Space ExplorationKuncai Zhong, Zexi Li, Weikang Qian. 346-351 [doi]
- Do Temperature and Humidity Exposures Hurt or Benefit Your SSDs?Adnan Maruf, Sashri Brahmakshatriya, Baolin Li, Devesh Tiwari, Gang Quan, Janki Bhimani. 352-357 [doi]
- SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped CoresFrancisco Bas, Pedro Benedicte, Sergi Alcaide, Guillem Cabo, Fabio Mazzocchetti, Jaume Abella 0001. 358-363 [doi]
- Is Approximation Universally Defensive Against Adversarial Attacks in Deep Neural Networks?Ayesha Siddique, Khaza Anuarul Hoque. 364-369 [doi]
- Reliability Analysis of a Spiking Neural Network Hardware AcceleratorTheofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos. 370-375 [doi]
- Reliability of Google's Tensor Processing Units for Embedded ApplicationsRubens Luiz Rech, Paolo Rech. 376-381 [doi]
- Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error ResilienceYoung Seo Lee, Gunjae Koo, Young-Ho Gong, Sung Woo Chung. 382-387 [doi]
- Accelerate Hardware Logging for Efficient Crash Consistency in Persistent MemoryZhiyuan Lu, Jianhui Yue, Yifu Deng, Yifeng Zhu. 388-393 [doi]
- MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D IntegrationMatheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini. 394-399 [doi]
- RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel RealignmentTing Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng. 400-405 [doi]
- SiC Processors for Extreme High- Temperature Venus Surface ExplorationHeewoo Kim, Javad Bagherzadeh, Ronald G. Dreslinski. 406-411 [doi]
- Unsupervised Test-Time Adaptation of Deep Neural Networks at the Edge: A Case StudyKshitij Bhardwaj, James Diffenderfer, Bhavya Kailkhura, Maya B. Gokhale. 412-417 [doi]
- Super-Efficient Super Resolution for Fast Adversarial Defense at the EdgeKartikeya Bhardwaj, Dibakar Gope, James Ward, Paul N. Whatmough, Danny Loh. 418-423 [doi]
- Fault-Tolerant Deep Neural Networks for Processing-In-Memory based Autonomous Edge SystemsSiyue Wang, Geng Yuan, Xiaolong Ma, Yanyu Li, Xue Lin, Bhavya Kailkhura. 424-429 [doi]
- FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation SystemsZishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury. 430-435 [doi]
- Improving Cell-Aware Test for Intra-Cell Short DefectsDong-Zhen Lee, Ying-Yen Chen, Kai-Chiang Wu, Mango C.-T. Chao. 436-441 [doi]
- APUF Faults: Impact, Testing, and DiagnosisYeqi Wei, Tim Fox, Vincent Dumoulin, Wenjing Rao, Natasha Devroye. 442-447 [doi]
- Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICsShao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty. 448-453 [doi]
- A Compaction Method for STLs for GPU in-field testJuan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 454-459 [doi]
- Automatic Generation of Architecture-Level Models from RTL Designs for Processors and AcceleratorsYu Zeng, Aarti Gupta, Sharad Malik. 460-465 [doi]
- Twine: A Chisel Extension for Component-Level Heterogeneous DesignShibo Chen, Yonathan Fisseha, Jean-Baptiste Jeannin, Todd M. Austin. 466-471 [doi]
- Towards Implementing RTL Microprocessor Agile Design Using Feature Oriented ProgrammingHongji Zou, Mingchuan Shi, Tun Li, WanXia Qu. 472-477 [doi]
- CSLE: A Cost-sensitive Learning Engine for Disk Failure Prediction in Large Data CentersXinyan Zhang, Kai Shant, Zhipeng Tan, Dan Feng. 478-483 [doi]
- Robust Binary Neural Network against Noisy Analog ComputationZong-Han Lee, Fu-Cheng Tsai, Shih-Chieh Chang. 484-489 [doi]
- MU-RMW: Minimizing Unnecessary RMW Operations in the Embedded Flash with SMR DiskChenlin Ma, Zhuokai Zhou, Yingping Wang, Yi Wang, Rui Mao 0001. 490-495 [doi]
- Optimizing CoW-based File Systems on Open-Channel SSDs with Persistent MemoryRunyu Zhang, Duo Liu, Chaoshu Yang, Xianzhang Chen, Lei Qiao, Yujuan Tan. 496-501 [doi]
- MCMQ: Simulation Framework for Scalable Multi-Core Flash Firmware of Multi-Queue SSDsJin Xue, Tianyu Wang, Zili Shao. 502-507 [doi]
- CR-Spectre: Defense-Aware ROP Injected Code-Reuse Based Dynamic SpectreAbhijitt Dhavlle, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao. 508-513 [doi]
- CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back BufferJongmin Lee, Jun-Yeon Lee, Taeweon Suh, Gunjae Koo. 514-519 [doi]
- SafeTEE: Combining Safety and Security on ARM-based MicrocontrollersMartin Schönstedt, Ferdinand Brasser, Patrick Jauernig, Emmanuel Stapf, Ahmad-Reza Sadeghi. 520-525 [doi]
- Using ontologies for dataset engineering in automotive AI applicationsMartin Herrmann, Christian Witt, Laureen Lake, Stefani Guneshka, Christian Heinzemann, Frank Bonarens, Patrick Feifel, Simon Funke. 526-531 [doi]
- Using Formal Conformance Testing to Generate Scenarios for Autonomous VehiclesJean-Baptiste Horel, Christian Laugier, Lina Marsso, Radu Mateescu 0001, Lucie Muller, Anshul Paigwar, Alessandro Renzaglia, Wendelin Serwe. 532-537 [doi]
- Remote Sensing with UAV and Mobile Recharging Vehicle RendezvousMichael H. Ostertag, Jason Ma, Tajana Rosing. 538-543 [doi]
- G-GPU: A Fully-Automated Generator of GPU-like ASIC AcceleratorsTiago D. Perez, Marcio M. Gonçalves, Leonardo Gobatto, Marcelo Brandalero, José Rodrigo Azambuja, Samuel Pagliarini. 544-547 [doi]
- Efficient Traveling Salesman Problem Solvers using the Ising Model with Simulated BifurcationTingting Zhang, Jie Han. 548-551 [doi]
- Providing Response Times Guarantees for Mixed-Criticality Network Slicing in 5GAndrea Nota, Selma Saidi, Dennis Overbeck, Fabian Kurtz, Christian Wietfeld. 552-555 [doi]
- SCI-FI: Control Signal, Code, and Control Flow Integrity against Fault Injection AttacksThomas Chamelot, Damien Couroussé, Karine Heydemann. 556-559 [doi]
- XTENSTORE: Fast Shielded In-memory Key-Value Store on a Hybrid x86-FPGA SystemHyunyoung Oh, Dongil Hwang, Maja Malenko, Myunghyun Cho, Hyungon Moon, Marcel Baunach, Yunheung Paek. 560-563 [doi]
- Learning to Mitigate Rowhammer AttacksBiresh Kumar Joardar, Tyler K. Bletsch, Krishnendu Chakrabarty. 564-567 [doi]
- Once For All Skip: Efficient Adaptive Deep Neural NetworksYu Yang, Di Liu, Hui Fang, Yi-Xiong Huang, Ying Sun, Zhi-Yuan Zhang. 568-571 [doi]
- Self-Aware MIMO Beamforming Systems: Dynamic Adaptation to Channel Conditions and Manufacturing VariabilitySuhasini Komarraju, Abhijit Chatterjee. 572-575 [doi]
- Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD PerformanceJunoh Moon, Mincheol Kang, Wonyoung Lee 0001, Soontae Kim. 576-579 [doi]
- SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM AcceleratorsSaurabh Tewari, Anshul Kumar, Kolin Paul. 580-583 [doi]
- NPU-Accelerated Imitation Learning for Thermal- and QoS-Aware Optimization of Heterogeneous Multi-CoresMartin Rapp, Nikita Krohmer, Heba Khdr, Jörg Henkel. 584-587 [doi]
- BMPQ: Bit-Gradient Sensitivity-Driven Mixed-Precision Quantization of DNNs from ScratchSouvik Kundu 0002, Shikai Wang, Qirui Sun, Peter A. Beerel, Massoud Pedram. 588-591 [doi]
- EM SCA & FI Self-Awareness and Resilience with Single On-chip Loop & ML ClassifiersArchisman Ghosh, Debayan Das, Santosh Ghosh, Shreyas Sen. 592-595 [doi]
- RTSEC: Automated RTL Code Augmentation for Hardware Security EnhancementOrlando Arias, Zhaoxiang Liu, Xiaolong Guo, Yier Jin, Shuo Wang. 596-599 [doi]
- Inter-IP Malicious Modification Detection through Static Information Flow TrackingZhaoxiang Liu, Orlando Arias, Weimin Fu, Yier Jin, Xiaolong Guo. 600-603 [doi]
- Many-Layer Hotspot Detection by Layer-Attentioned Visual Question AnsweringYen-Shuo Chen, Iris Hui-Ru Jiang. 604-607 [doi]
- RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based MulticoreYanshul Sharma, Sanjay Moulik, Shounak Chakraborty 0001. 608-611 [doi]
- Online Performance and Power Prediction for Edge TPU via Comprehensive CharacterizationYang Ni, Yeseong Kim, Tajana Rosing, Mohsen Imani. 612-615 [doi]
- Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario MethodologyJi-Yung Lin, Pieter Weckx, Subrat Mishra, Alessio Spessot, Francky Catthoor. 616-621 [doi]
- Analyzing CAN's Timing under Periodically Authenticated EncryptionMingqing Zhang, Philip Parsch, Henry Hoffmann, Alejandro Masrur. 620-623 [doi]
- Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep LearningUtkarsh Saxena, Indranil Chakraborty, Kaushik Roy 0001. 624-627 [doi]
- Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCsTim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker 0001, Juan Miguel De Haro Ruiz, Daniel Jiménez-González, Miquel Moretó, Carlos Álvarez 0001, Jesús Labarta, Imen Baili. 628-631 [doi]
- Towards Approximate Computing for Achieving Energy vs. Accuracy Trade-offsAleksandr Ometov, Jari Nurmi. 632-635 [doi]
- The SELENE Deep Learning Acceleration Framework for Safety-related ApplicationsLaura Medina, Salva Carrion, Pablo Andreu, Tomás Picornell, Jose Flich, Carles Hernández, Michael Sandoval, Markel Sainz, Charles-Alexis Lefebvre, Martin Rönnbäck, Martin Matschnig, Matthias Wess, Herbert Taucher. 636-639 [doi]
- Adaptive Droplet Routing for MEDA Biochips via Deep Reinforcement LearningMahmoud Elfar, Tung-Che Liang, Krishnendu Chakrabarty, Miroslav Pajic. 640-645 [doi]
- Contamination-Free Switch Design and Synthesis for Microfluidic Large-Scale IntegrationDuan Shen, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 646-651 [doi]
- Exploiting Parallelism with Vertex-Clustering in Processing-In-Memory-based GCN AcceleratorsYu Zhu, Zhenhua Zhu, Guohao Dai, Kai Zhong, Huazhong Yang, Yu Wang 0002. 652-657 [doi]
- Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPULing Liang, Zhaodong Chen, Lei Deng 0003, Fengbin Tu, Guoqi Li, Yuan Xie 0001. 658-663 [doi]
- HyperSpike: HyperDimensional Computing for More Efficient and Robust Spiking Neural NetworksJustin Morris, Hin-Wai Lui, Kenneth Stewart, Behnam Khaleghi, Anthony Thomas, Thiago Marback, Baris Aksanli, Emre Neftci, Tajana Rosing. 664-669 [doi]
- A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design TimeHedi Fendri, Marco Macchetti, Jérôme Perrine, Mirjana Stojilovic. 670-675 [doi]
- A Cross-Platform Cache Timing Attack Framework via Deep LearningRuyi Ding, Ziyue Zhang, Xiang Zhang, Cheng Gongye, Yunsi Fei, Aidong Adam Ding. 676-681 [doi]
- Design of AI Trojans for Evading Machine Learning-based Detection of Hardware TrojansZhixin Pan, Prabhat Mishra 0001. 682-687 [doi]
- DIP Learning on CAS-Lock: Using Distinguishing Input Patterns for Attacking Logic LockingAkashdeep Saha, Urbi Chatterjee, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty. 688-693 [doi]
- MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link PredictionLilas Alrahis, Satwik Patnaik, Muhammad Shafique 0001, Ozgur Sinanoglu. 694-699 [doi]
- DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention ArchitectureTao Yang, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, Li Jiang 0002. 700-705 [doi]
- Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNsNael Fasfous, Lukas Frickenstein, Michael Neumeier, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Maurizio Martina, Walter Stechele. 706-711 [doi]
- Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIMZihao Deng, Michael Orshansky. 712-717 [doi]
- Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?Gourav Datta, Peter A. Beerel. 718-723 [doi]
- Value-aware Parity Insertion ECC for Fault-tolerant Deep Neural NetworkSeo-Seok Lee, Joon-Sung Yang. 724-729 [doi]
- A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on EdgeKai Li, Junzhuo Zhou, Yuhang Wang, Junyi Luo, Zhengke Yang, Shuxin Yang, Wei Mao, Mingqiang Huang, Hao Yu 0001. 730-735 [doi]
- Ternarized TCN for $\mu \mathrm{J}/\text{Inference}$ Gesture Recognition from DVS Event FramesGeorg Rutishauser, Moritz Scherer, Tim Fischer, Luca Benini. 736-741 [doi]
- REH: Redesigning Extendible Hashing for Commercial Non-Volatile MemoryZhengtao Li, Zhipeng Tan, Jianxi Chen. 742-747 [doi]
- Memory Management Methodology for Application Data Structure Refinement and Placement on Heterogeneous DRAM/NVM SystemsManolis Katsaragakis, Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris. 748-753 [doi]
- MicroFaaS: Energy-efficient Serverless on Bare-metal Single-board ComputersAnthony Byrne, Yanni Pang, Allen Zou, Shripad Nadgowda, Ayse K. Coskun. 754-759 [doi]
- FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph SchedulerSiting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu 0001. 760-765 [doi]
- TRADER: A Practical Track-Assignment-Based Detailed RouterZhen Zhuang, Genggeng Liu, Tsung-Yi Ho, Bei Yu, Wenzhong Guo. 766-771 [doi]
- CR&P: An Efficient Co-operation between Routing and PlacementErfan Aghaeekiasaraee, Aysa Fakheri Tabrizi, Tiago Augusto Fontana, Renan Netto, Sheiny Fabre Almeida, Upma Gandh, José Luís Gützel, David T. Westwick, Laleh Behja. 772-777 [doi]
- Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction ModelSuwan Kim, Taewhan Kim. 778-783 [doi]
- Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous SystemsHaoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu 0001. 784-789 [doi]
- A Comprehensive Solution for Securing Connected and Autonomous VehiclesMohsin Kamal, Christos Kyrkou, Nikos Piperigkos, Andreas Papandreou, Andreas Kloukiniotis, Jordi Casademont, Natlia Porras Mateu, Daniel Baos Castillo, Rodrigo Diaz Rodriguez, Nicola Gregorio Durante, Peter Hofmann, Petros Kapsalas, Aris S. Lalos, Konstantinos Moustakas, Christos Laoudias, Theocharis Theocharides, Georgios Ellinas. 790-795 [doi]
- Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor SolutionsBernhard Lippmann, Ann-Christin Bette, Matthias Ludwig 0005, Johannes Mutter, Johanna Baehr, Alexander Hepp, Horst A. Gieser, Nicola Kovac, Tobias Zweifel, Martin Rasche, Oliver Kellermann. 796-801 [doi]
- De-RISC: A Complete RISC-V Based Space-Grade PlatformNils-Johan Wessman, Fabio Malatesta, Stefano Ribes, Jan Andersson, Antonio García-Vilanova, Miguel Masmano, Vicente Nicolau, Paco Gomez, Jimmy Le Rhun, Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Fabio Mazzocchetti, Jaume Abella 0001. 802-807 [doi]
- The Scale4Edge RISC-V EcosystemWolfgang Ecker, Peer Adelt, Wolfgang Müller 0003, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer 0001, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker 0001, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann 0001, Mihaela Damian, Julian Oppermann, Andreas Koch 0001, Jörg Bormann, Johannes Partzsch, Christian Mayr 0001, Wolfgang Kunz. 808-813 [doi]
- Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware DesignsAngeliki Kritikakou, Olivier Sentieys, Guillaume Hubert, Youri Helen, Jean-Francois Coulon, Patrice Deroux-Dauphin. 819-824 [doi]
- SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based ConvolutionsAlfio Di Mauro, Arpan Suravi Prasad, Zhikai Huang, Matteo Spallanzani, Francesco Conti 0001, Luca Benini. 825-830 [doi]
- LRP: Predictive output activation based on SVD approach for CNN s accelerationXinxin Wu, Zhihua Fan, Tianyu Liu, Wenming Li, Xiaochun Ye, Dongrui Fan. 831-836 [doi]
- Exploiting Architecture Advances for Sparse Solvers in Circuit SimulationZhiyuan Yan, Biwei Xie, Xingquan Li, Yungang Bao. 837-842 [doi]
- Data-Aware Cache Management for Graph AnalyticsNeelam Sharma, Varun Venkitaraman, Newton, Vikash Kumar, Shubham Singhania, Chandan Kumar Jha 0004. 843-848 [doi]
- AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore SystemsKe Wang 0030, Hao Zheng 0005, Yuan Li, Jiajun Li, Ahmed Louri. 849-854 [doi]
- PIMProf: An Automated Program Profiler for Processing-in-Memory Offloading DecisionsYizhou Wei, Minxuan Zhou, Sihang Liu 0001, Korakit Seemakhupt, Tajana Rosing, Samira Manabi Khan. 855-860 [doi]
- Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural NetworksKarthikeyan Nagarajan, Junde Li, Sina Sayyah Ensan, Mohammad Nasim Imtiaz Khan, Sachhidh Kannan, Swaroop Ghosh. 861-866 [doi]
- Gibbon: Efficient Co-Exploration of NN Model and Processing-In-Memory ArchitectureHanbo Sun, Chenyu Wang, Zhenhua Zhu, Xuefei Ning, Guohao Dai, Huazhong Yang, Yu Wang 0002. 867-872 [doi]
- AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication AcceleratorSaeed Seyedfaraji, Baset Mesgari, Semeen Rehman. 873-878 [doi]
- Characterizing and Optimizing Hybrid DRAM-PM Main Memory System with Application AwarenessYongfeng Wang, Yinjin Fu, Yubo Liu, Zhiguang Chen, Nong Xiao. 879-884 [doi]
- PATS: Taming Bandwidth Contention between Persistent and Dynamic MemoriesShucheng Wang, Qiang Cao, Ziyi Lu, Hong Jiang 0001, Yuanyuan Dong. 885-890 [doi]
- Unifying Temporal and Spatial Locality for Cache Management inside SSDsZhibing Sha, Zhigang Cai, François Trahay, Jianwei Liao, Dong Yin. 891-896 [doi]
- DWR: Differential Wearing for Read Performance Optimization on High-Density NAND Flash MemoryYunpeng Song, Qiao Li 0001, Yina Lv, Changlong Li, Liang Shi. 897-902 [doi]
- GATLB: A Granularity-Aware TLB to Support Multi-Granularity Pages in Hybrid Memory SystemYujuan Tan, Yujie Xie, Zhulin Ma, Zhichao Yan, Zhichao Zhang, Duo Liu, Xianzhang Chen. 903-908 [doi]
- OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the EdgeTianyu Jia, En-Yu Yang, Yu-Shun Hsiao, Jonathan J. Cruz, David Brooks 0001, Gu-Yeon Wei, Vijay Janapa Reddi. 909-914 [doi]
- An FPGA Overlay for Efficient Real-Time Localization in 1/10th Scale Autonomous VehiclesAndrea Bernardi, Gianluca Brilli, Alessandro Capotondi, Andrea Marongiu, Paolo Burgio. 915-920 [doi]
- Enabling Fast Deep Learning on Tiny Energy-Harvesting IoT DevicesSahidul Islam, Jieren Deng, Shanglin Zhou, Chen Pan, Caiwen Ding, Mimi Xie. 921-926 [doi]
- Emulation of Non-volatile Digital Logic for Batteryless Intermittent ComputingSimone Ruffini, Kasim Sinan Yildirim, Davide Brunelli. 927-932 [doi]
- A Systematic Removal of Minimum Implant Area Violations under Timing ConstraintEunsol Jeong, Heechun Park, Taewhan Kim. 933-938 [doi]
- DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net WeightingPeiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu 0001. 939-944 [doi]
- EventTimer: Fast and Accurate Event-Based Dynamic Timing AnalysisZuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang. 945-950 [doi]
- Practical Substrate Design Considering Symmetrical and Shielding RoutesHao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho. 951-956 [doi]
- NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the FutureMelvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler 0005, R. Walied Ahmad, Alexander Krüger, Leticia Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Lemme, Rainer Leupers, Rainer Waser. 957-962 [doi]
- VEDLIoT: Very Efficient Deep Learning in IoTMartin Kaiser, René Griessl, Nils Kucza, C. Haumann, Lennart Tigges, K. Mika, Jens Hagemeyer, Florian Porrmann, Ulrich Rückert 0001, Micha vor dem Berge, Stefan Krupop, Mario Porrmann, Marco Tassemeier, Pedro Trancoso, F. Qararyah, S. Zouzoula, António Casimiro, Alysson Neves Bessani, José Cecílio, S. Andersson, Oliver Brunnegård, Olof Eriksson, R. Weiss, F. Mcierhöfer, Hans Salomonsson, E. Malekzadeh, D. Ödman, A. Khurshid, Pascal Felber, Marcelo Pasin, Valerio Schiavoni, Jämes Ménétrey, K. Gugala, P. Zierhoffer, Eric Knauss, Hans-Martin Heyn. 963-968 [doi]
- Intelligent Methods for Test and ReliabilityHussam Amrouch, J. Anders, S. Becker, M. Betka, G. Bleher, P. Domanski, N. Elhamawy, T. Ertl, A. Gatzastras, Paul R. Genssler, S. Hasler, M. Heinrich, A. van Hoorn, H. Jafarzadeh, I. Kallfass, Florian Klemme, S. Koch, R. Küsters, A. Lalama, R. Latty, Y. Liao, Natalia Lylina, Z. Najafi Haghi, D. Pflüger, Ilia Polian, J. Rivoir, M. Sauer, D. Schwachhofer, S. Templin, C. Volmer, S. Wagner, D. Weiskopf, H.-J. Wunderlich, B. Yang, M. Zimmermann. 969-974 [doi]
- EVOLVE: Towards Converging Big-Data, High-Performance and Cloud-Computing WorldsAchilleas Tzenetopoulos, Dimosthenis Masouros, Konstantina Koliogeorgi, Sotirios Xydis, Dimitrios Soudris, Antony Chazapis, Christos Kozanitis, Angelos Bilas, Christian Pinto, Huy Nam Nguyen, Stelios Louloudakis, Georgios Gardikis, George Vamvakas, Michelle Aubrun, Christi Symeonidou, Vassilis Spitadakis, Konstantinos Xylogiannopoulos, Bernhard Peischl, Tahir Emre Kalayci, Alexander Stocker, Jean-Thomas Acquaviva. 975-980 [doi]
- SDK4ED: One-click platform for Energy-aware, Maintainable and Dependable ApplicationsCharalampos Marantos, Miltiadis G. Siavvas, Dimitrios Tsoukalas, Christos P. Lamprakos, Lazaros Papadopoulos, Pawel Boryszko, Katarzyna Filus, Joanna Domanska, Apostolos Ampatzoglou, Alexander Chatzigeorgiou, Erol Gelenbe, Dionisis D. Kehagias, Dimitrios Soudris. 981-986 [doi]
- ADD-based Spectral Analysis of Probing SecurityMaria Chiara Molteni, Vittorio Zaccaria, Valentina Ciriani. 987-992 [doi]
- Guaranteed Activation of Capacitive Trojan Triggers During Post Production Test via Supply PulsingBora Bilgic, Sule Ozev. 993-998 [doi]
- FPGA-to-CPU Undervolting AttacksDina G. Mahmoud, Samah Hussein, Vincent Lenders, Mirjana Stojilovic. 999-1004 [doi]
- Beware of the Bias - Statistical Performance Evaluation of Higher-Order Alphabet PUFsChristoph Frisch, Michael Pehl. 1005-1010 [doi]
- Design of Many-Core Big Little µBrains for Energy-Efficient Embedded Neuromorphic ComputingM. Lakshmi Varshika, Adarsha Balaji, Federico Corradi, Anup Das 0001, Jan Stuijt, Francky Catthoor. 1011-1016 [doi]
- Hydra: A near hybrid memory accelerator for CNN inferencePalash Das, Ajay Joshi, Hemangee K. Kapoor. 1017-1022 [doi]
- TCX: A Programmable Tensor ProcessorTailin Liang, Lei Wang, Shaobo Shi, John Glossner, Xiaotong Zhang. 1023-1028 [doi]
- A Flash-based Current-mode IC to Realize Quantized Neural NetworksKyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula. 1029-1034 [doi]
- NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural NetworkFuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li. 1035-1040 [doi]
- Full-credit Flow Control: A Novel Technique to Implement Deadlock-free Adaptive RoutingYi Dai, Kai Lu, Sheng Ma, Junsheng Chang. 1041-1046 [doi]
- DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet NetworksEbadollah Taheri, Sudeep Pasricha, Mahdi Nikdast. 1047-1052 [doi]
- Non-Volatile Phase Change Material based Nanophotonic InterconnectParya Zolfaghari, Joel Ortiz, Cédric Killian, Sébastien Le Beux. 1053-1058 [doi]
- A Reliability Concern on Photonic Neural NetworksYinyi Liu, Jiaxu Zhang, Jun Feng 0008, Shixi Chen, Jiang Xu 0001. 1059-1064 [doi]
- How Parallel Circuit Execution Can Be Useful for NISQ Computing?Siyuan Niu, Aida Todri-Sanial. 1065-1070 [doi]
- Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual PortsRyosuke Matsuo, Shin-ichi Minato. 1071-1076 [doi]
- Design and Evaluation Frameworks for Advanced RISC-based Ternary ProcessorDongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee. 1077-1082 [doi]
- Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology NodeJan Lappas, André Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn. 1083-1084 [doi]
- SafeSU-2: a Safe Statistics Unit for Space MPSoCsGuillem Cabo, Sergi Alcaide, Carles Hernández, Pedro Benedicte, Francisco Bas, Fabio Mazzocchetti, Jaume Abella 0001. 1085-1086 [doi]
- Efficient Global Robustness Certification of Neural Networks via Interleaving Twin-Network EncodingZhilu Wang, Chao Huang 0015, Qi Zhu 0002. 1087-1092 [doi]
- Opportunistic Communication with Latency Guarantees for Intermittently-Powered DevicesKacper Wardega, Wenchao Li, Hyoseung Kim, Yawen Wu, Zhenge Jia, Jingtong Hu. 1093-1098 [doi]
- RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCsYvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti 0001. 1099-1102 [doi]
- Increasing Cellular Network Energy Efficiency for Railway CorridorsAdrian Schumacher, Ruben Merz, Andreas Burg. 1103-1106 [doi]
- Health Monitoring of Milling Tools under Distinct Operating Conditions by a Deep Convolutional Neural Network modelPriscile Suawa Fogou, Michael Hübner 0001. 1107-1110 [doi]
- Gradient-based Bit Encoding Optimization for Noise-Robust Binary Memristive CrossbarYoungeun Kim, Hyunsoo Kim, Seijoon Kim, Sang Joon Kim, Priyadarshini Panda. 1111-1114 [doi]
- TAS: Ternarized Neural Architecture Search for Resource-Constrained Edge DevicesMohammad Loni, Hamid Mousavi, Mohammad Riazati, Masoud Daneshtalab, Mikael Sjödin. 1115-1118 [doi]
- Examining and Mitigating the Impact of Crossbar Non-idealities for Accurate Implementation of Sparse Deep Neural NetworksAbhiroop Bhattacharjee, Lakshya Bhatnagar, Priyadarshini Panda. 1119-1122 [doi]
- Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided AgingNiklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler. 1123-1126 [doi]
- Hardware Acceleration of Explainable Machine LearningZhixin Pan, Prabhat Mishra 0001. 1127-1130 [doi]
- Fast simulation of future 128-bit architecturesFabien Portas, Frédéric Pétrot. 1131-1134 [doi]
- A Generative AI for Heterogeneous Network-on-Chip Design Space PruningMaxime Mirka, Maxime France-Pillois, Gilles Sassatelli, Abdoulaye Gamatié. 1135-1138 [doi]
- SPARROW: A Low-Cost Hardware/Software Co-designed SIMD Microarchitecture for AI Operations in Space ProcessorsMarc Solé Bonet, Leonidas Kosmidis. 1139-1142 [doi]
- A Pluggable Vector Unit for RISC-V Vector ExtensionVincenzo Maisto, Alessandro Cilardo. 1143-1148 [doi]
- Robust Reconfigurable Scan NetworksNatalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich. 1149-1152 [doi]
- SyncLock: RF Transceiver Security Using Synchronization LockingAlán Rodrigo Díaz Rizo, Hassan Aboushady, Haralampos-G. Stratigopoulos. 1153-1156 [doi]
- Deep Reinforcement Learning for Analog Circuit Structure SynthesisZhenxin Zhao, Lihong Zhang. 1157-1160 [doi]
- Compatibility Checking for Autonomous Lane-Changing Assistance SystemsPo-Yu Huang, Kai-Wei Liu, Zong-Lun Li, Sanggu Park, Edward Andert, Chung-Wei Lin, Aviral Shrivastava. 1161-1164 [doi]
- PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNsPengfei Huang, Chenghua Wang, Ke Chen 0018, Weiqiang Liu. 1165-1168 [doi]
- LAC: Learned Approximate ComputingVaibhav Gupta, Tianmu Li, Puneet Gupta 0001. 1169-1172 [doi]
- Eva-CAM: A Circuit/Architecture-Level Evaluation Tool for General Content Addressable MemoriesLiu Liu, Mohammad Mehdi Sharifi, Ramin Rajaei, Arman Kazemi, Kai Ni 0004, Xunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu. 1173-1176 [doi]
- Hybrid Digital-Digital In-Memory ComputingMuhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Fan Yao, Rickard Ewetz. 1177-1180 [doi]
- NeuroHammer: Inducing Bit-Flips in Memristive Crossbar MemoriesFelix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers. 1181-1184 [doi]
- A Low-Cost Methodology for EM Fault Emulation on FPGAPaolo Maistri, Jiayun Po. 1185-1188 [doi]
- Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology NodesShayesteh Masoumian, Georgios N. Selimis, Rui Wang, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil. 1189-1192 [doi]
- BOiLS: Bayesian Optimisation for Logic SynthesisAntoine Grosnit, Cédric Malherbe, Rasul Tutunov, Xingchen Wan, Jun Wang 0012, Haitham Bou-Ammar. 1193-1196 [doi]
- Accurate Probabilistic Miss Ratio Curve Approximation for Adaptive Cache Allocation in Block Storage SystemsRongshang Li, Yingtian Tang, Qiquan Shi, Hui Mao, Lei Chen 0031, Jikun Jin, Peng Lu, Zhuo Cheng. 1197-1202 [doi]
- SGRM: Stackelberg Game-Based Resource Management for Edge Computing SystemsAntonis Karteris, Manolis Katsaragakis, Dimosthenis Masouros, Dimitrios Soudris. 1203-1208 [doi]
- Runtime Energy Minimization of Distributed Many-Core Systems using Transfer LearningDainius Jenkus, Fei Xia, Rishad A. Shafik, Alex Yakovlev. 1209-1214 [doi]
- Siamese Neural Encoders for Long-Term Indoor Localization with Mobile DevicesSaideep Tiku, Sudeep Pasricha. 1215-1220 [doi]
- Discrete Samplers for Approximate Inference in Probabilistic Machine LearningShirui Zhao, Nimish Shah, Wannes Meert, Marian Verhelst. 1221-1226 [doi]
- HELCFL: High-Efficiency and Low-Cost Federated Learning in Heterogeneous Mobile-Edge ComputingYangguang Cui, Kun Cao, Junlong Zhou, Tongquan Wei. 1227-1232 [doi]
- Efficient Hotspot Detection via Graph Neural NetworkShuyuan Sun, Yiyang Jiang, Fan Yang 0001, Bei Yu 0001, Xuan Zeng 0001. 1233-1238 [doi]
- FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation FunctionsBehnam Ghavami, Mani Sadati, Zhenman Fang, Lesley Shannon. 1239-1244 [doi]
- WRAP: Weight RemApping and Processing in RRAM-based Neural Network Accelerators Considering Thermal EffectPo-Yuan Chen, Fang-Yi Gu, Yu-Hong Huang, Ing-Chao Lin. 1245-1250 [doi]
- Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic ComputingZongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, Li Jiang 0002. 1251-1256 [doi]
- SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation EnvironmentsAibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui 0004, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. 1257-1262 [doi]
- Leakage Power Analysis in Different S-Box Masking Protection SchemesJavad Bahrami, Mohammad Ebrahimabadi, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi. 1263-1268 [doi]
- Cache-aware Schedulability Analysis of PREM Compliant TasksSyed Aftab Rashid, Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Eduardo Tovar. 1269-1274 [doi]
- Reconciling QoS and Concurrency in NVIDIA GPUs via Warp-Level SchedulingJayati Singh, Ignacio Sañudo Olmedo, Nicola Capodieci, Andrea Marongiu, Marco Caccamo. 1275-1280 [doi]
- Counting Priority Inversions: Computing Maximum Additional Core Requests of DAG TasksMorteza Mohaqeqi, Gaoyang Dai, Wang Yi 0001. 1281-1286 [doi]
- Shyper: An embedded hypervisor applying hierarchical resource isolation strategies for mixed-criticality systemsYicong Shen, Lei Wang, Yuanzhi Liang, Siran Li, Bo Jiang. 1287-1292 [doi]
- Response Time Analysis for Energy-Harvesting Mixed-Criticality SystemsKankan Wang, Yuhan Lin, Qingxu Deng. 1293-1298 [doi]
- Latency analysis of self-suspending task chainsTomasz Kloda, Jiyang Chen, Antoine Bertout, Lui Sha, Marco Caccamo. 1299-1304 [doi]
- Counteract Side-Channel Analysis of Neural Networks by ShufflingManuel Brosch, Matthias Probst, Georg Sigl. 1305-1310 [doi]
- Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICsShao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty. 1311-1316 [doi]
- Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module GraphsAlexander Hepp, Johanna Baehr, Georg Sigl. 1317-1322 [doi]
- JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong CorruptionLeon Li, Alex Orailoglu. 1323-1328 [doi]
- TriLock: IC Protection with Tunable Corruptibility and Resilience to SAT and Removal AttacksYuke Zhang, Yinghua Hu, Pierluigi Nuzzo, Peter A. Beerel. 1329-1334 [doi]
- Understanding and Mitigating Memory Interference in FPGA-based HeSoCsGianluca Brilli, Alessandro Capotondi, Paolo Burgio, Andrea Marongiu. 1335-1340 [doi]
- PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNsZhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, YongHong Tian. 1341-1346 [doi]
- Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFSLei Mo, Qi Zhou, Angeliki Kritikakou, Ji Liu. 1347-1352 [doi]
- coxHE: A software-hardware co-design framework for FPGA acceleration of homomorphic computationMingqin Han, Yilan Zhu, Qian Lou, Zimeng Zhou, Shanqing Guo, Lei Ju. 1353-1358 [doi]
- A Composable Design Space Exploration Framework to Optimize Behavioral LockingLuca Collini, Ramesh Karri, Christian Pilato. 1359-1364 [doi]
- DIET: A Dynamic Energy Management Approach for Wearable Health Monitoring DevicesNuzhat Yamin, Ganapati Bhat, Janardhan Rao Doppa. 1365-1370 [doi]
- Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement LearningLin Chen, Xiao Li, Jiang Xu. 1371-1376 [doi]
- CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved PerformanceLokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda. 1377-1382 [doi]
- Thermal- and Cache-Aware Resource Management based on ML- Driven Cache Contention PredictionMohammed Bakr Sikal, Heba Khdr, Martin Rapp, Jörg Henkel. 1384-1388 [doi]
- T-SKID: Predicting When to Prefetch Separately from Address PredictionToru Koizumi 0001, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya. 1389-1394 [doi]
- LiM-HDL: HDL-Based Synthesis for In-Memory ComputingSaman Fröhlich, Rolf Drechsler. 1395-1400 [doi]
- Triple-Skipping Near-MRAM Computing Framework for AIoT EraJuntong Chen, Hao Cai, Bo Liu 0019, Jun Yang 0006. 1401-1406 [doi]
- Achieving Crash Consistency by Employing Persistent L1 CacheAkshay Krishna Ramanathan, Sara Mahdizadeh-Shahri, Yi Xiao, Vijaykrishnan Narayanan. 1407-1412 [doi]
- Referencing-in-Array Scheme for RRAM-based CIM ArchitectureAbhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui. 1413-1418 [doi]
- BMC+Fuzz: Efficient and Effective Test GenerationRavindra Metta, Raveendra Kumar Medicherla, Samarjit Chakraborty. 1419-1424 [doi]
- Dolmen: FPGA Swarm for Safety and Liveness VerificationEmilien Fournier, Ciprian Teodorov, Loïc Lagadec. 1425-1430 [doi]
- Adding Dual Variables to Algebraic Reasoning for Gate-Level Multiplier VerificationDaniela Kaufmann, Paul Beame, Armin Biere, Jakob Nordström. 1431-1436 [doi]
- On the Optimal OBDD Representation of 2-XOR Boolean Affine SpacesAnna Bernasconi 0001, Valentina Ciriani, Marco Longhi. 1437-1442 [doi]
- Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture RecognitionAlessio Burrello, Francesco Bianco Morghet, Moritz Scherer, Simone Benatti, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari. 1443-1448 [doi]
- INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure DetectionLorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi. 1449-1454 [doi]
- AMSER: Adaptive Multimodal Sensing for Energy Efficient and Resilient eHealth SystemsEmad Kasaeyan Naeini, Sina Shahhosseini, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani, Nikil D. Dutt. 1455-1460 [doi]
- A Simple Hybrid Model for Accurate Delay Modeling of a Multi-Input GateArman Ferdowsi, Jürgen Maier 0002, Daniel Öhlinger, Ulrich Schmid 0001. 1461-1466 [doi]
- SySCIM: SystemC-AMS Simulation of Memristive Computation In-MemorySeyed Hossein Hashemi Shadmehri, Ali BanaGozar, Mehdi Kamal, Sander Stuijk, Ali Afzali-Kusha, Massoud Pedram, Henk Corporaal. 1467-1472 [doi]
- PiMulator: a Fast and Flexible Processing-in-Memory Emulation PlatformSergiu Mosanu, Mohammad Nazmus Sakib, Tommy Tracy, Ersin Cukurtas, Alif Ahmed, Preslav Ivanov, Samira Khan, Kevin Skadron, Mircea Stan. 1473-1478 [doi]
- BenQ: Benchmarking Automated Quantization on Deep Neural Network AcceleratorsZheng Wei, Xingjun Zhang, Jingbo Li, Zeyu Ji, Jia Wei. 1479-1484 [doi]
- GraphHD: Efficient graph classification using hyperdimensional computingIgor Nunes, Mike Heddes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum. 1485-1490 [doi]
- DeepPM: Transformer-based Power and Performance Prediction for Energy-Aware SoftwareJun S. Shim, Bogyeong Han, Yeseong Kim, Jihong Kim 0001. 1491-1496 [doi]
- Quantization-Aware In-situ Training for Reliable and Accurate Edge AIJoão Paulo C. de Lima, Luigi Carro. 1497-1502 [doi]
- ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural NetworksMyeongjae Jang, Jinkwon Kim, Jesung Kim, Soontae Kim. 1503-1508 [doi]
- PREFENDER: A Prefetching Defender against Cache Side Channel Attacks as A PretenderLuyi Li, Jiayi Huang, Lang Feng, Zhongfeng Wang. 1509-1514 [doi]
- Stealthy Inference Attack on DNN via Cache-based Side-Channel AttacksHan Wang, Syed Mahbub Hafiz, Kartik Patwari, Chen-Nee Chuah, Zubair Shafiq, Houman Homayoun. 1515-1520 [doi]
- Know Your Neighbor: Physically Locating Xeon Processor Cores on the Core Tile GridHyungmin Cho. 1521-1526 [doi]
- RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption LibraryFurkan Aydin, Emre Karabulut, Seetal Potluri, Erdem Alkim, Aydin Aysu. 1527-1532 [doi]