Yu Zeng, Aarti Gupta, Sharad Malik. Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators. In Cristiana Bolchini, Ingrid Verbauwhede, Ioana Vatajelu, editors, 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022. pages 460-465, IEEE, 2022. [doi]
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