Abstract is missing.
- 2 Ambient Light-Driven Solar Cell-Powered Biofuel Cell-Input Biosensing System with LED Driving for Stand-Alone RF-Less Continuous Glucose Monitoring Contact LensGuowei Chen, XinYang Yu, Yue Wang, Tran Minh Quan, Naofumi Matsuyama, Takuya Tsujimura, Kiichi Niitsu. 1-2 [doi]
- A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna ArrayTaikun Ma, Wei Deng 0001, Haikun Jia, Yejun He, Baoyong Chi. 3-4 [doi]
- A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face OrientationReiji Miura, Saito Shibata, Masahiro Usui, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda. 5-6 [doi]
- A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke PatientsTay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang. 7-8 [doi]
- A Side-Channel Hardware Trojan in 65nm CMOS with $2\mu\mathrm{W}$ precision and Multi-bit Leakage CapabilityTiago D. Perez, Samuel Pagliarini. 9-10 [doi]
- SC-K9: A Self-synchronizing Framework to Counter Micro-architectural Side ChannelsHongyu Fang, Milos Doroslovacki, Guru Venkataramani. 11-18 [doi]
- CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper)Zihan Xu, Lingfeng Yin, Yongqiang Lyu, Haixia Wang, Gang Qu 0001, Dongsheng Wang 0002. 19-24 [doi]
- Lightweight and Secure Branch Predictors against Spectre AttacksCongcong Chen, Chaoqun Shen, Jiliang Zhang 0002. 25-30 [doi]
- Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and ChallengesMd Tanvir Arafin. 31-36 [doi]
- HEALM: Hardware-Efficient Approximate Logarithmic Multiplier with Reduced ErrorShuyuan Yu, Maliha Tasnim, Sheldon X.-D. Tan. 37-42 [doi]
- DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image ClassificationDehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano. 43-49 [doi]
- Thermal-Aware Layout Optimization and Mapping Methods for Resistive Neuromorphic EnginesChengrui Zhang, Yu Ma, Pingqiang Zhou. 50-55 [doi]
- NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric ChipsHsin-Chuan Huang, Chi-Chun Liang, Qining Wang, Xing Huang, Tsung-Yi Ho, Chang-Jin Kim 0001. 56-61 [doi]
- Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple FaultsJian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho. 62-67 [doi]
- Improving the Robustness of Microfluidic NetworksGerold Fink, Philipp Ebner, Sudip Poddar, Robert Wille. 68-73 [doi]
- An Efficient Kriging-based Constrained Multi-objective Evolutionary Algorithm for Analog Circuit Synthesis via Self-adaptive Incremental LearningSen Yin, Wenfei Hu, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Yan Wang. 74-79 [doi]
- Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary AlgorithmLing-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang. 80-85 [doi]
- A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-TestbenchJingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang 0001, Xuan Zeng 0001, Dian Zhou. 86-91 [doi]
- A 2.17μW@120fps Ultra-Low-Power Dual-Mode CMOS Image Sensor with Senputing ArchitectureZiwei Li, Han Xu, Zheyu Liu, Li Luo, Qi Wei 0001, Fei Qiao. 92-93 [doi]
- A Reconfigurable Inference Processor for Recurrent Neural Networks Based on Programmable Data Format in a Resource-Limited FPGAJiho Kim, Kwoanyoung Park, Tae-Hwan Kim. 94-95 [doi]
- Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOSTomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine. 96-97 [doi]
- Deformable Chiplet-Based Computer Using Inductively Coupled Wireless CommunicationJunichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai. 98-99 [doi]
- Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning AlgorithmsShiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen. 100-107 [doi]
- Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper)Keren Zhu 0001, Hao Chen, Mingjie Liu, David Z. Pan. 108-113 [doi]
- Common-Centroid Layout for Active and Passive Devices: A Review and the Road AheadNibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar. 114-121 [doi]
- PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model SupportChung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang. 122-127 [doi]
- RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture SearchZheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi. 128-133 [doi]
- A Heuristic Exploration of Retraining-free Weight-Sharing for CNN CompressionEtienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio. 134-139 [doi]
- HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and ComputationXinheng Liu, Yao Chen, Prakhar Ganesh, Junhao Pan, Jinjun Xiong, Deming Chen. 140-146 [doi]
- Mapping Large Scale Finite Element Computing on to Wafer-Scale EnginesYishuang Lin, Rongjian Liang, Yaguang Li, Hailiang Hu, Jiang Hu. 147-153 [doi]
- Generalizing Tandem Simulation: Connecting High-level and RTL Simulation ModelsYue Xing, Aarti Gupta, Sharad Malik. 154-159 [doi]
- Automated Detection of Spatial Memory Safety Violations for Constrained DevicesSören Tempel, Vladimir Herdt, Rolf Drechsler. 160-165 [doi]
- Lithography Hotspot Detection via Heterogeneous Federated Learning with Local AdaptationXuezhong Lin, Jingyu Pan, Jinming Xu 0002, Yiran Chen, Cheng Zhuo. 166-171 [doi]
- Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask VerificationXiqiong Bai, Ziran Zhu, Peng Zou, Jianli Chen, Jun Yu, Yao-Wen Chang. 172-177 [doi]
- Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous IntegrationSung Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang. 178-183 [doi]
- Pre-Routing Path Delay Estimation Based on Transformer and Residual FrameworkTai Yang, Guoqing He, Peng Cao. 184-189 [doi]
- Efficient Critical Paths Search Algorithm using Mergeable HeapKexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin. 190-195 [doi]
- A Graph Neural Network Method for Fast ECO Leakage Power OptimizationKai Wang, Peng Cao. 196-201 [doi]
- Vector-based Dynamic IR-drop Prediction Using Machine LearningJia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chien-Mo James Li, Norman Chang, Ying Shiun Li, Wentze Chuang. 202-207 [doi]
- Fast Electromigration Stress Analysis Considering Spatial Joule Heating EffectsMohammadamir Kavousi, Liang Chen, Sheldon X.-D. Tan. 208-213 [doi]
- SONIC: A Sparse Neural Network Inference Accelerator with Silicon Photonics for Energy-Efficient Deep LearningFebin Sunny, Mahdi Nikdast, Sudeep Pasricha. 214-219 [doi]
- XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized TrainingJaeyoung Kang 0001, Behnam Khaleghi, Yeseong Kim, Tajana Rosing. 220-225 [doi]
- HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product EngineQidong Tang, Zhezhi He, Fangxin Liu, Zongwu Wang, Yiyuan Zhou, Yinghuan Zhang, Li Jiang 0002. 226-231 [doi]
- SYNTHNET: A High-throughput yet Energy-efficient Combinational Logic Neural NetworkTianen Chen, Taylor Kemp, Younghyun Kim 0001. 232-237 [doi]
- Optimal Data Allocation for Graph Processing in Processing-in-Memory SystemsZerun Li, Xiaoming Chen, Yinhe Han. 238-243 [doi]
- Boosting the Search Performance of B+-tree with Sentinels for Non-volatile MemoryChongnan Ye, Chundong Wang 0001. 244-249 [doi]
- Algorithm and Hardware Co-design for Reconfigurable CNN AcceleratorHongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk. 250-255 [doi]
- Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction SchedulingCan Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen. 256-261 [doi]
- Time-Triggered Scheduling for Time-Sensitive Networking with PreemptionYuanbin Zhou, Soheil Samii, Petru Eles, Zebo Peng. 262-267 [doi]
- A Task Parallelism Runtime Solution for Deep Learning Applications using MPSoC on Edge DevicesHua Jiang, Raghav Chakravarthy, Ravikumar V. Chakaravarthy. 268-274 [doi]
- Circuit and System Technologies for Energy-Efficient Edge Robotics: (Invited Paper)Zishen Wan, Ashwin Sanjay Lele, Arijit Raychowdhury. 275-280 [doi]
- RTL Regression Test Selection using Machine LearningGanapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar. 281-287 [doi]
- Net Separation-Oriented Printed Circuit Board Placement via Margin MaximizationChung-Kuan Cheng, Chia-Tung Ho, Chester Holtz. 288-293 [doi]
- HybridGP: Global Placement for Hybrid-Row-Height DesignsKuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang. 294-299 [doi]
- DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning ToolkitRachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan. 300-306 [doi]
- Linear Feedback Shift Register Reseeding for Stochastic Circuit Repairing and MinimizationChen Wang, Weikang Qian. 307-313 [doi]
- BSC: Block-based Stochastic Computing to Enable Accurate and Efficient TinyMLYuhong Song, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Rui Xu, Yongzhuo Zhang, Bingzhe Li, Lei Yang. 314-319 [doi]
- Streaming Accuracy: Characterizing Early Termination in Stochastic ComputingHsuan Hsiao, Joshua San Miguel, Jason Helge Anderson. 320-325 [doi]
- TENET: Temporal CNN with Attention for Anomaly Detection in Automotive Cyber-Physical SystemsSooryaa Vignesh Thiruloga, Vipin Kumar Kukkala, Sudeep Pasricha. 326-331 [doi]
- ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life EnhancementHanqing Zhu, Jiaqi Gu, Chenghao Feng, Mingjie Liu, Zixuan Jiang, Ray T. Chen, David Z. Pan. 332-338 [doi]
- Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory TechniqueXiaoming Chen, Yinhe Han. 339-344 [doi]
- SonicFFT: A system architecture for ultrasonic-based FFT accelerationDarayus Adil Patel, Viet Phuong Bui, Kevin Tshun Chuan Chai, Amit Lal, Mohamed M. Sabry Aly. 345-351 [doi]
- FirVer: Concolic Testing for Systematic Validation of Firmware BinariesTashfia Alam, Zhenkun Yang, Bo Chen, Nicholas Armour, Sandip Ray. 352-357 [doi]
- WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and DebuggingLucas Klemmer, Daniel Große. 358-364 [doi]
- Accelerate SAT-based ATPG via Preprocessing and New Conflict Management HeuristicsJunhua Huang, Hui-Ling Zhen, Naixing Wang, Mingxuan Yuan, Hui Mao, Yu Huang, Jiping Tao. 365-370 [doi]
- A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine LearningMohamed Saleh Abouelyazid, Sherif Hammouda, Yehea Ismail. 371-376 [doi]
- Lamina: Low Overhead Wear Leveling for NVM with Bounded TailJiaCheng Huang, Min Peng, Libing Wu, Chun Jason Xue, Qingan Li. 377-382 [doi]
- Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT ApplicationsKangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang. 383-388 [doi]
- Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency HidingRui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yuhong Song, Jingzhi Lin. 389-394 [doi]
- Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets ResynthesisHeinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli. 395-402 [doi]
- Delay Optimization of Combinational Logic by AND-OR Path RestructuringUlrich Brenner, Anna Silvanus. 403-409 [doi]
- A Versatile Mapping Approach for Technology Mapping and Graph OptimizationAlessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar 0001, Giovanni De Micheli. 410-416 [doi]
- Avatar: Reinforcing Fault Attack Countermeasures in EDA with Fault TransformationsPrithwish Basu Roy, Patanjali SLPSK, Chester Rebeiro. 417-422 [doi]
- Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOIMariam Tlili, Alhassan Sayed, Doaa Mahmoud, Marie-Minerve Louërat, Hassan Aboushady, Haralampos-G. Stratigopoulos. 423-428 [doi]
- Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design TechniquesSajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler. 429-435 [doi]
- Dynamic CNN Accelerator Supporting Efficient Filter Generator with Kernel Enhancement and Online Channel PruningChen Tang, Wenyu Sun, Wenxun Wang, Yongpan Liu. 436-441 [doi]
- Toward Low-Bit Neural Network Training Accelerator by Dynamic Group AccumulationYixiong Yang, Ruoyang Liu, Wenyu Sun, Jinshan Yue, Huazhong Yang, Yongpan Liu. 442-447 [doi]
- An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural NetworksLiuyao Dai, Quan Cheng, Yuhang Wang, Gengbin Huang, Junzhuo Zhou, Kai Li, Wei Mao, Hao Yu 0001. 448-453 [doi]
- Multi-Precision Deep Neural Network Acceleration on FPGAsNegar Neda, Salim Ullah, Azam Ghanbari, Hoda Mahdiani, Mehdi Modarressi, Akash Kumar 0001. 454-459 [doi]
- Efficient Preparation of Cyclic Quantum StatesFereshte Mozafari, Yuxiang Yang, Giovanni De Micheli. 460-465 [doi]
- Limiting the Search Space in Optimal Quantum Circuit MappingLukas Burgholzer, Sarah Schneider, Robert Wille. 466-471 [doi]
- Efficient Routing in Coarse-Grained Reconfigurable Arrays Using Multi-Pole NEM RelaysAkash Levy, Michael Oduoza, Akhilesh Balasingam, Roger T. Howe, Priyanka Raina. 472-478 [doi]
- Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAsKangwei Xu, Yuanqing Cheng. 479-484 [doi]
- Fast Thermal Analysis for Chiplet Design based on Graph Convolution NetworksLiang Chen, Wentian Jin, Sheldon X.-D. Tan. 485-492 [doi]
- Design Close to the Edge for Advanced Technology using Machine Learning and Brain-Inspired AlgorithmsHussam Amrouch, Florian Klemme, Paul R. Genssler. 493-499 [doi]
- Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper)Ahmet F. Budak, Zixuan Jiang, Keren Zhu 0001, Azalia Mirhoseini, Anna Goldie, David Z. Pan. 500-505 [doi]
- Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System LevelFelix Last, Ceren Yeni, Ulf Schlichtmann. 506-512 [doi]
- Transient Adjoint DAE Sensitivities: a Complete, Rigorous, and Numerically Accurate FormulationNaomi Sagan, Jaijeet Roychowdhury. 513-518 [doi]
- Generative-Adversarial-Network-Guided Well-Aware Placement for Analog CircuitsKeren Zhu 0001, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan. 519-525 [doi]
- TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation ArchitectureShiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen. 526-531 [doi]
- Efficient Computer Vision on Edge Devices with Pipeline-Parallel Hierarchical Neural NetworksAbhinav Goel, Caleb Tung, Xiao Hu, George K. Thiruvathukal, James C. Davis, Yung-Hsiang Lu. 532-537 [doi]
- Efficient On-Device Incremental Learning by Weight FreezingZe-Han Wang, Zhenli He, Hui Fang, Yi-Xiong Huang, Ying Sun, Yu Yang, Zhi-Yuan Zhang, Di Liu. 538-543 [doi]
- $\text{Edge}^{n}$ AI: Distributed Inference with Local Edge Devices and Minimal LatencyMaedeh Hemmat, Azadeh Davoodi, Yu Hen Hu. 544-549 [doi]
- Large Forests and Where to "Partially" Fit ThemAndrea Damiani, Emanuele Del Sozzo, Marco D. Santambrogio. 550-555 [doi]
- AdaSens: Adaptive Environment Monitoring by Coordinating Intermittently-Powered SensorsShuyue Lan, Zhilu Wang, John Mamish, Josiah D. Hester, Qi Zhu 0002. 556-561 [doi]
- Energy Harvesting Aware Multi-Hop Routing Policy in Distributed IoT System Based on Multi-Agent Reinforcement LearningWen Zhang, Tao Liu, Mimi Xie, Longzhuang Li, Dulal Kar, Chen Pan. 562-567 [doi]
- An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic MultipliersLingxiao Hou, Yutaka Masuda, Tohru Ishihara. 568-573 [doi]
- Neural Network Pruning and Fast Training for DRL-based UAV Trajectory PlanningYilan Li, Haowen Fang, Mingyang Li, Yue Ma, Qinru Qiu. 574-579 [doi]
- High-Correlation 3D Routability Estimation for Congestion-guided Global RoutingMiaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang. 580-585 [doi]
- SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacityJiayuan He 0003, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali. 586-591 [doi]
- FPGA-Accelerated Maze Routing Kernel for VLSI DesignsXun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang. 592-597 [doi]
- Reliable Memristive Neural Network Accelerators Based on Early Denoising and Sparsity InductionAnlan Yu, Ning Lyu, Wujie Wen, Zhiyuan Yan. 598-603 [doi]
- Boosting ReRAM-based DNN by Row Activation OversubscriptionMengyu Guo, Zihan Zhang, Jianfei Jiang, Qin Wang, Naifeng Jing. 604-609 [doi]
- XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task AdaptionFan Zhang, Li Yang, Jian Meng, Yu Kevin Cao, Jae-sun Seo, Deliang Fan. 610-615 [doi]
- CGRA Mapping Using Zero-Suppressed Binary Decision DiagramsRami Beidas, Jason Helge Anderson. 616-622 [doi]
- Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLSM. Imtiaz Rashid, Benjamin Carrión Schäfer. 623-628 [doi]
- Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis SchedulingBenjamin Carrión Schäfer. 629-634 [doi]
- Techniques for CAD Tool Parameter Auto-tuning in Physical Synthesis: A Survey (Invited Paper)Hao Geng, Tinghuan Chen, Qi Sun, Bei Yu 0001. 635-640 [doi]
- Application of Deep Learning in Back-End Simulation: Challenges and OpportunitiesYufei Chen, Haojie Pei, Xiao Dong, Zhou Jin, Cheng Zhuo. 641-646 [doi]
- EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper)Jiaxi Zhang 0001, Qiuyang Gao, Yijiang Guo, Bizhao Shi, Guojie Luo. 647-653 [doi]
- DVFSspy: Using Dynamic Voltage and Frequency Scaling as a Covert Channel for Multiple ProceduresPengfei Qiu, Dongsheng Wang 0002, Yongqiang Lyu, Gang Qu 0001. 654-659 [doi]
- FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital DesignsA. V. Lakshmy, Chester Rebeiro, Swarup Bhunia. 660-665 [doi]
- Data Leakage through Self-Terminated Write Schemes in Memristive CachesJonas Krautter, Mahta Mayahinia, Dennis R. E. Gnad, Mehdi B. Tahoori. 666-671 [doi]
- A Voltage Template Attack on the Modular Polynomial Subtraction in KyberJianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li 0001, Yuan Cao. 672-677 [doi]
- FeMIC: Multi-Operands in-Memory Computing Based on FeFETsRui Liu, Xiaoyu Zhang, Xiaoming Chen, Yinhe Han, Minghua Tang. 678-683 [doi]
- Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADCYuxuan Huang, Yifan He, Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu. 684-689 [doi]
- STREAM: Towards READ-based In-Memory Computing for Streaming based Data ProcessingMuhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha 0001, Fan Yao, Rickard Ewetz. 690-695 [doi]
- On the Viability of Decision Trees for Learning Models of SystemsSwantje Plambeck, Lutz Schammer, Görschwin Fey. 696-701 [doi]
- This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN AcceleratorYen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai. 702-707 [doi]
- HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNsHao Kong, Di Liu, Xiangzhong Luo, Weichen Liu, Ravi Subramaniam. 708-713 [doi]
- Pearl: Towards Optimization of DNN-accelerators Via Closed-Form Analytical RepresentationArko Dutt, Suprojit Nandy, Mohamed M. Sabry. 714-719 [doi]