Table of Contents

• Automated Design of ChipletsAlberto L. Sangiovanni-Vincentelli, Zheng Liang, Zhe Zhou, Jiaxi Zhang 0001. 1-8 [doi]
• FastPass: Fast Pin Access Analysis with Incremental SAT SolvingFangzhou Wang, Jinwei Liu, Evangeline F. Y. Young. 9-16 [doi]
• Pin Access-Oriented Concurrent Detailed RoutingYun-Jhe Jiang, Shao-Yun Fang. 17-25 [doi]
• Reinforcement Learning Guided Detailed Routing for Custom CircuitsHao Chen 0059, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu 0001, David Z. Pan, Haoxing Ren. 26-34 [doi]
• Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery NetworkJai-Ming Lin, Yu-Tien Chen, Yang-Tai Kung, Hao-Jia Lin. 35-43 [doi]
• NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability ModelChia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren. 44-52 [doi]
• FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay LinesMeng Lian, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 53-61 [doi]
• On Legalization of Die Bonding Bumps and Pads for 3D ICsSai Pentapati, Anthony Agnesina, Moritz Brunion, Yen-Hsiang Huang, Sung Kyu Lim. 62-70 [doi]
• Reshaping System Design in 3D Integration: Perspectives and ChallengesHung-Ming Chen, Chu-Wen Ho, Shih-Hsien Wu, Wei Lu, Po-Tsang Huang, Hao-Ju Chang, Chien-Nan Jimmy Liu. 71-77 [doi]
• Co-design for Heterogeneous Integration: A Failure Analysis PerspectiveErica Douglas, Julia Deitz, Timothy Ruggles, Daniel Perry, Damion Cummings, Mark Rodriguez, Nichole Valdez, Brad Boyce. 78-79 [doi]
• Goal Driven PCB Synthesis Using Machine Learning and CloudScale ComputeTaylor Hogan. 80 [doi]
• Gate-All-Around Technology is Coming.: What's Next After GAA?Victor Moroz. 81 [doi]
• VLSIR - A Modular Framework for Programming Analog & Custom Circuits & LayoutsDan Fritchman. 82-83 [doi]
• Joint Optimization of Sizing and Layout for AMS Designs: Challenges and OpportunitiesAhmet Faruk Budak, Keren Zhu 0001, Hao Chen, Souradip Poddar, Linran Zhao, Yaoyao Jia, David Z. Pan. 84-92 [doi]
• Learning from the Implicit Functional Hierarchy in an Analog NetlistHelmut Graeb, Markus Leibl. 93-100 [doi]
• The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open IssuesSachin S. Sapatnekar. 101-102 [doi]
• Analog Layout Automation On Advanced Process TechnologiesSoner Yaldiz. 103 [doi]
• Immersion and EUV Lithography: Two Pillars to Sustain Single-Digit Nanometer NodesBurn J. Lin. 104 [doi]
• Advanced Design Methodologies for Directed Self-AssemblyShao-Yun Fang. 105 [doi]
• Challenges for Interconnect Reliability: From Element to System LevelOlalla Varela Pedreira, Houman Zahedmanesh, Youqi Ding, Ivan Ciofi, Kristof Croes. 106 [doi]
• Combined Modeling of Electromigration, Thermal and Stress Migration in AC Interconnect LinesSusann Rothe, Jens Lienig. 107-114 [doi]
• Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment InterconnectsNestor E. Evmorfopoulos, Mohammad Abdullah Al Shohel, Olympia Axelou, Pavlos Stoikos, Vidya A. Chhabria, Sachin S. Sapatnekar. 115-123 [doi]
• Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature DistributionArmen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau. 124-132 [doi]
• Placement Initialization via Sequential Subspace Optimization with Sphere ConstraintsPengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang. 133-140 [doi]
• DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial LearningYi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, Sung Kyu Lim. 141-148 [doi]
• AutoDMP: Automated DREAMPlace-based Macro PlacementAnthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing Ren. 149-157 [doi]
• Assessment of Reinforcement Learning for Macro PlacementChung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang. 158-166 [doi]
• GPU Acceleration in Physical SynthesisEvangeline F. Y. Young. 167 [doi]
• Efficient Runtime Power Modeling with On-Chip Power MetersZhiyao Xie. 168-174 [doi]
• DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAsRachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan. 175-184 [doi]
• Building Oscillatory Neural Networks: AI Applications and Physical Design ChallengesAida Todri-Sanial. 185-186 [doi]
• Optimization of AI SoC with Compiler-assisted Virtual Design PlatformChih-Tsun Huang, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang. 187-193 [doi]
• Challenges and Opportunities for Computing-in-Memory ChipsXiang Qiu. 194 [doi]
• Neural Operators for Solving PDEs and Inverse DesignAnima Anandkumar. 195 [doi]
• Quantum Challenges for EDALeon Stok. 196 [doi]
• Developing Quantum Workloads for Workload-Driven Co-designAnne Matsuura. 197 [doi]
• MQT QMAP: Efficient Quantum Circuit MappingRobert Wille, Lukas Burgholzer. 198-204 [doi]
• EDA for Domain Specific Computing: An Introduction for the PanelIris Hui-Ru Jiang, David G. Chinnery. 205 [doi]
• Software-driven Design for Domain-specific ComputeDesmond A. Kirkpatrick. 206 [doi]
• Google Investment in Open Source Custom Hardware Development Including No-Cost Shuttle ProgramTim Ansell. 207 [doi]
• A Case for Open EDA VerticalsZhiru Zhang, Matthew Hofmann, Andrew Butt. 208-209 [doi]
• Addressing the EDA Roadblocks for Domain-specific Compilers: An Industry PerspectiveAlireza Kaviani. 210 [doi]
• High-level Synthesis for Domain Specific ComputingHanchen Ye, HyeGang Jun, Jin Yang, Deming Chen. 211-219 [doi]
• Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection AttacksJhih-Wei Hsu, Kuan-Cheng Chen, Yan-Syuan Chen, Yu-Hsiang Lo, Yao-Wen Chang. 220-228 [doi]
• Security Closure of IC Layouts Against Hardware TrojansFangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang 0007, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young. 229-237 [doi]
• X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel AttacksSaideep Sreekumar, Mohammed Ashraf, Mohammed Thari Nabeel, Ozgur Sinanoglu, Johann Knechtel. 238-246 [doi]
• Validating the Redundancy Assumption for HDL from Code Clone's PerspectiveJianjun Xu, Jiayu He, Jingyan Zhang, Deheng Yang, Jiang Wu, Xiaoguang Mao. 247-255 [doi]
• Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 ContestMohammad Eslami, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri, Samuel Pagliarini. 256-264 [doi]
• ISPD 2023 Lifetime Achievement Award BioMalgorzata Marek-Sadowska. 265 [doi]