Abstract is missing.
- A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW ArchitecturesThomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia. 4-13 [doi]
- Integrating a Misprediction Recovery Cache (MRC) into a Superscalar PipelineJames O. Bondi, Ashwini K. Nanda, Simonjit Dutta. 14-23 [doi]
- Trace Cache: A Low Latency Approach to High Bandwidth Instruction FetchingEric Rotenberg, Steve Bennett, James E. Smith. 24-35 [doi]
- Accurate and Practical Profile-driven Compilation Using the Profile BufferThomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch. 36-45 [doi]
- Efficient Path ProfilingThomas Ball, James R. Larus. 46-57 [doi]
- Profile-driven Instruction Level Parallel Scheduling with Application to Super BlocksChandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker. 58-67 [doi]
- Speculative Hedge: Regulating Compile-time Speculation Against Profile VariationsBrian L. Deitrich, Wen-mei W. Hwu. 70-79 [doi]
- Hot Cold Optimization of Large Windows/NT ApplicationsRobert S. Cohn, P. Geoffrey Lowney. 80-89 [doi]
- Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary ResultsCheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei W. Hwu. 90-99 [doi]
- Analysis Techniques for Predicated CodeRichard Johnson, Michael S. Schlansker. 100-113 [doi]
- Global Predicate Analysis and Its Application to Register AllocationDavid M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker. 114-125 [doi]
- Modulo Scheduling of Loops in Control-intensive Non-numeric ProgramsDaniel M. Lavery, Wen-mei W. Hwu. 126-137 [doi]
- Assigning Confidence to Conditional Branch PredictionsErik Jacobsen, Eric Rotenberg, James E. Smith. 142-152 [doi]
- Wrong-path Instruction PrefetchingJim Pierce, Trevor N. Mudge. 165-175 [doi]
- Design Decisions Influencing the UltraSPARC s Instruction Fetch ArchitectureRobert Yung. 178-190 [doi]
- Increasing the Instruction Fetch Rate via Block-structured Instruction Set ArchitecturesEric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt. 191-200 [doi]
- Instruction Fetch Mechanisms for VLIW Architectures with Compressed EncodingsThomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye. 201-211 [doi]
- Tango: A Hardware-Based Data Prefetching Technique for Superscalar ProcessorsShlomit S. Pinter, Adi Yoaz. 214-225 [doi]
- Exceeding the Dataflow Limit via Value PredictionMikko H. Lipasti, John Paul Shen. 226-237 [doi]
- The Performance Potential of Data Dependence Speculation & CollapsingYiannakis Sazeides, Stamatis Vassiliadis, James E. Smith. 238-247 [doi]
- Heuristics for Register-Constrained Software PipeliningJosep Llosa, Mateo Valero, Eduard Ayguadé. 250-261 [doi]
- Instruction Scheduling and Executable EditingEric Schnarr, James R. Larus. 288-297 [doi]
- Instruction Scheduling for the HP PA-8000David A. Dunn, Wei-Chung Hsu. 298-307 [doi]
- Meld Scheduling: Relaxing Scheduling Constraints Across Region BoundariesSantosh G. Abraham, Vinod Kathail, Brian L. Deitrich. 308-321 [doi]
- Custom-fit Processors: Letting Applications Define ArchitecturesJoseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli. 324-335 [doi]
- Optimization for a Superscalar Out-of-Order MachineAnne M. Holler. 336-348 [doi]
- Optimization of Machine Descriptions for Efficient UseJohn C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau. 349-358 [doi]