Table of Contents

• Dataflow supercomputingMichael J. Flynn, Oliver Pell, Oskar Mencer. 1-3 [doi]
• Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filteringDoris Chen, Deshanand P. Singh. 5-12 [doi]
• Detecting power attacks on reconfigurable hardwareAdrien Le Masle, Wayne Luk. 14-19 [doi]
• Efficient and side-channel-secure block cipher implementation with custom instructions on FPGASuvarna Mane, Mostafa M. I. Taha, Patrick Schaumont. 20-25 [doi]
• CRUSH: Cognitive Radio Universal Software HardwareGeorge Eichinger, Kaushik Chowdhury, Miriam Leeser. 26-32 [doi]
• Data coding functions for Software Defined Radios implemented on R3TOSRaul Torrego, Inaki Val, Eñaut Muxika, Xabier Iturbe, Khaled Benkrid. 33-40 [doi]
• EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chipChirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings. 41-48 [doi]
• Limitations of incremental signal-tracing for FPGA debugEddie Hung, Steven J. E. Wilton. 49-56 [doi]
• SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfigurationFlorian Devic, Lionel Torres, Jérémie Crenne, Benoît Badrignans, Pascal Benoit. 57-62 [doi]
• FPGAs for trusted cloud computingKen Eguro, Ramarathnam Venkatesan. 63-70 [doi]
• Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAsCarl Ingemarsson, Petter Kallstrom, Oscar Gustafsson. 71-74 [doi]
• Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resourcesMichael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele. 75-82 [doi]
• On the difficulty of pin-to-wire routing in FPGAsNiyati Shah, Jonathan Rose. 83-90 [doi]
• Routing algorithms for FPGAS with sparse intra-cluster routing crossbarsYehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk. 91-98 [doi]
• Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case studyBrahim Betkaoui, Yu Wang 0002, David B. Thomas, Wayne Luk. 99-104 [doi]
• Bio-inspired walking: A FPGA multicore system for a legged robotMichael Henrey, Sean Edmond, Lesley Shannon, Carlo Menon. 105-111 [doi]
• A scalable FPGA-based design for field programmable large-scale ion channel simulationsGraeme Coapes, Terrence S. T. Mak, Junwen Luo, Alex Yakovlev, Chi-Sang Poon. 112-119 [doi]
• Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computationYoshiaki Kono, Kentaro Sano, Satoru Yamamoto. 120-127 [doi]
• FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometryZoltán Nagy, Csaba Nemes, Antal Hiba, András Kiss, Árpád Csík, Péter Szolgay. 128-135 [doi]
• Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamicsTakayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 136-142 [doi]
• Analytical placement for heterogeneous FPGAsMarcel Gort, Jason Helge Anderson. 143-150 [doi]
• Profiling FPGA floor-planning effects on timing closureJaren Lamprecht, Brad L. Hutchings. 151-156 [doi]
• Multi-kernel floorplanning for enhanced CGRASAaron Wood, Adam Knight, Benjamin Ylvisaker, Scott Hauck. 157-164 [doi]
• Optimising explicit finite difference option pricing for dynamic constant reconfigurationQiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas. 165-172 [doi]
• Exploiting run-time reconfiguration in stencil computationXinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell. 173-180 [doi]
• A two step hardware design method using CλaSHRinse Wester, Christiaan Baaij, Jan Kuper. 181-188 [doi]
• Convey vector personalities - FPGA acceleration with an openmp-like programming effort?Björn Meyer, Jörn Schumacher, Christian Plessl, Jens Forstner. 189-196 [doi]
• Improving memory support in the VTR flowAndrew Somerville, Kenneth B. Kent. 197-202 [doi]
• Verification of streaming designs by combining symbolic simulation and equivalence checkingTim Todman, Wayne Luk. 203-208 [doi]
• Hardware implementation of MRF map inference on an FPGA platformJungwook Choi, Rob A. Rutenbar. 209-216 [doi]
• CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filtersAtabak Mahram, Martin C. Herbordt. 217-223 [doi]
• Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP supportEric Matthews, Lesley Shannon, Alexandra Fedorova. 224-230 [doi]
• Automating the design of mLUT MPSoPC FPGAs in the cloudEugene Cartwright, Azad Fahkari, Sen Ma, Christina Smith, Miaoqing Huang, David L. Andrews, Jason Agron. 231-236 [doi]
• A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functionsTakashi Takenaka, Masamichi Takagi, Hiroaki Inoue. 237-242 [doi]
• Hardware implementation of motion blur removalThusitha N. Chandrapala, Amila P. Cabral, Sapumal Ahangama, Thilina S. Ambagahawaththa, Jayathu G. Samarawickrama. 243-248 [doi]
• Correctly rounded floating-point division for DSP-enabled FPGAsBogdan Pasca. 249-254 [doi]
• Reduced complexity single and multiple constant multiplication in floating point precisionMartin Kumm, Katharina Liebisch, Peter Zipf. 255-261 [doi]
• FPGA-based design and implementation of a multi-GBPS LDPC decoderAlexios Balatsoukas-Stimming, Apostolos Dollas. 262-269 [doi]
• Optimizing packet lookup in time and space on FPGAThilan Ganegedara, Viktor K. Prasanna, Gordon J. Brebner. 270-276 [doi]
• Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systemsRodrigo Bernardo, Luis R. Monte, Eduardo Mobilon, Valentino Corso, Arley H. Salvador, Carolina G. Neves, Cleber A. Nakandakare, Daniele R. da Silva, Luis P. F. de Barros, Ronaldo F. da Silva. 277-283 [doi]
• High-level aging estimation for FPGA-mapped designsAbdulazim Amouri, Mehdi Baradaran Tahoori. 284-291 [doi]
• Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environmentsJaime Espinosa, David de Andrés, Juan Carlos Ruiz, Pedro J. Gil. 292-299 [doi]
• Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systemsAdam Jacobs, Grzegorz Cieslewski, Alan D. George. 300-306 [doi]
• Automatically exploiting regularity in applications to reduce reconfiguration memory requirementsFatma Abouelella, Karel Bruneel, Dirk Stroobandt. 307-314 [doi]
• Mapping logic to reconfigurable FPGA routingKarel Heyse, Karel Bruneel, Dirk Stroobandt. 315-321 [doi]
• Maximizing the reuse of routing resources in a reconfiguration-aware connection routerElias Vansteenkiste, Karel Bruneel, Dirk Stroobandt. 322-329 [doi]
• Random decision tree body part recognition using FPGAsJason Oberg, Ken Eguro, Ray Bittner, Alessandro Forin. 330-337 [doi]
• Acceleration of distance-to-default with hardware-software co-designIzaan Allugundu, Pranay Puranik, Yat Piu Lo, Akash Kumar. 338-344 [doi]
• An efficient hardware architecture of the optimised SIFT descriptor generationWenjuan Deng, Yiqun Zhu, Hao Feng, Zhiguo Jiang. 345-352 [doi]
• Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable ArrayRobin Panda, Carl Ebeling, Scott Hauck. 353-360 [doi]
• A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment functionTakashi Yoza, Minoru Watanabe. 361-366 [doi]
• Non-volatile 3D stacking RRAM-based FPGAYi-Chung Chen, Wenhua Wang, Hai Li, Wei Zhang. 367-372 [doi]
• Intra-chip physical parameter sensor for FPGAS using flip-flop metastabilityGhaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev. 373-379 [doi]
• A novel microprocessor-intrinsic Physical Unclonable FunctionAbhranil Maiti, Patrick Schaumont. 380-387 [doi]
• FPGA based key generation technique for anti-counterfeiting methods using Physically Unclonable Functions and artificial intelligenceSwetha Pappala, Mohammed Y. Niamat, Weiqing Sun. 388-393 [doi]
• DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGASAntoni Roca, José Flich, Giorgos Dimitrakopoulos. 394-399 [doi]
• An area-efficient partially reconfigurable crossbar switch with low reconfiguration delayChin Hau Hoo, Akash Kumar. 400-406 [doi]
• An acceleration of a graph cut segmentation with FPGADaichi Kobori, Tsutomu Maruyama. 407-413 [doi]
• An FPGA acceleration of a level set segmentation methodHaruhisa Tsuyama, Tsutomu Maruyama. 414-420 [doi]
• A high performance, open source SATA2 coreAshwin A. Mendon, Bin Huang, Ron Sass. 421-428 [doi]
• IP-XACT extensions for IP interoperability guarantees and software model generationThomas P. Perry, Richard L. Walke, Rob Payne, Stefan Petko, Khaled Benkrid. 429-436 [doi]
• K-means implementation on FPGA for high-dimensional data using triangle inequalityZhongduo Lin, Charles Lo, Paul Chow. 437-442 [doi]
• Enhancing performance of Tall-Skinny QR factorization using FPGAsAbid Rafique, Nachiket Kapre, George A. Constantinides. 443-450 [doi]
• Real-time corner and polygon detection system on FPGAChunmeng Bi, Tsutomu Maruyama. 451-457 [doi]
• Deep-pipelined FPGA implementation of ellipse estimation for eye trackingKeisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata, Kiyoshi Oguri. 458-463 [doi]
• A Benign Hardware Trojan on FPGA-based embedded systemsJason Xin Zheng, Ethan Chen, Miodrag Potkonjak. 464-470 [doi]
• A resiliency-aware scheduling approach for FPGA configuration: Preliminary resultsJeremy Abramson, Pedro C. Diniz. 471-472 [doi]
• Power/performance optimization in FPGA-based asymmetric multi-core systemsBruno de Abreu Silva, Vanderlei Bonato. 473-474 [doi]
• Thermal-aware partitioning for 3D FPGAsKrishna Chaitanya Nunna, Farhad Mehdipour, Kazuaki Murakami. 475-476 [doi]
• Reconfigurable multi-processor architecture for streaming applicationsLeyla S. Ghazanfari, Roberto Airoldi, Jari Nurmi, Tapani Ahonen. 477-478 [doi]
• NoC-AXI interface for FPGA-based MPSoC platformsMarco Ramírez, Masoud Daneshtalab, Juha Plosila, Pasi Liljeberg. 479-480 [doi]
• Modeling of dynamic reconfigurable systems with HaskellBahram N. Uchevler, Kjetil Svarstad. 481-482 [doi]
• Stimulation board for automated verification of touchscreen-based devicesIvan Kastelan, Vladimir Marinkovic, Radomir Dzakula, Nikola Vranic, Vukota Pekovic. 483-484 [doi]
• High level structural description of streaming applicationsAnja Niedermeier, Jan Kuper, Gerard J. M. Smit. 485-486 [doi]
• Ambient hardware and the case for transcoding media streamsMilica Orlandic, Kjetil Svarstad. 487-488 [doi]
• Combining data and computation transformations for fine-grain reconfigurable architecturesCristiano B. Oliveira, Eduardo Marques. 489-490 [doi]
• Implementation and outcomes of FPGA-based system design in Mongolian educationD. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner. 491-494 [doi]
• CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCSChao Wang, Xi Li, Junneng Zhang, Peng Chen 0004, Xuehai Zhou. 495-498 [doi]
• Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanismJunichi Sawada, Hiroaki Nishi. 499-502 [doi]
• Dataflow graph partitioning for high level synthesisSharad Sinha, Thambipillai Srikanthan. 503-506 [doi]
• A fast and high quality stereo matching algorithm on FPGAMinxi Jin, Tsutomu Maruyama. 507-510 [doi]
• An FPGA aligner for short read mappingYupeng Chen, Bertil Schmidt, Douglas L. Maskell. 511-514 [doi]
• Raising the abstraction level of HDL for control-dominant applicationsMarc-André Daigneault, Jean-Pierre David. 515-518 [doi]
• A two-stage variation-aware placement method for FPGAS exploiting variation maps classificationZhenyu Guan, Justin S. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung. 519-522 [doi]
• Speedy bus mastering PCI expressRay Bittner. 523-526 [doi]
• Adaptive Sequential Monte Carlo approach for real-time applicationsThomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski. 527-530 [doi]
• From opencl to high-performance hardware on FPGASTomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, Deshanand P. Singh. 531-534 [doi]
• A framework for Open Tiled Manycore System-On-ChipStefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild, Andreas Herkersdorf. 535-538 [doi]
• Fault detection and avoidance of FPGA in various granularitiesKazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 539-542 [doi]
• CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnectYusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura. 543-546 [doi]
• Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfigurationRuben Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina. 547-550 [doi]
• Development of an FPGA-based real-time P300 spellerKanav Khurana, Pooja Gupta, Rajesh Chandrasekhara Panicker, Akash Kumar. 551-554 [doi]
• Influence of operating conditions on ring oscillator-based entropy sources in FPGAsChristian Hochberger, Changgong Li, Michael Raitza, Markus Vogt. 555-558 [doi]
• Exploration of ring oscillator design space for temperature measurements on FPGAsChristoph Ruething, Andreas Agne, Markus Happe, Christian Plessl. 559-562 [doi]
• Extending BORPH for shared memory reconfigurable computersChangqing Xun, Mei Wen, Nan Wu 0003, Chunyuan Zhang, Hayden Kwok-Hay So. 563-566 [doi]
• Automatic generation of application-specific accelerators for FPGAs from python loop nestsDavid Sheffield, Michael J. Anderson, Kurt Keutzer. 567-570 [doi]
• PPMC: Hardware scheduling and memory management support for multi acceleratorsTassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé. 571-574 [doi]
• Performance analysis of fully-adaptable CRC accelerators on an FPGAAmila Akagic, Hideharu Amano. 575-578 [doi]
• Dynamic multiobjective optimization management of the Energy-Performance-Accuracy space for separable 2-D complex filtersDaniel Llamocca, Cesar Carranza, Marios S. Pattichis. 579-582 [doi]
• HCM: An abstraction layer for seamless programming of DPR FPGAYan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric Pétrot. 583-586 [doi]
• Early performance estimation of image compression methods on soft processorsAdam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung. 587-590 [doi]
• Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging systemMichael Kunz, Martin Kumm, Martin Heide, Peter Zipf. 591-594 [doi]
• Sliding block Viterbi decoders in FPGAMário P. Véstias, Horácio C. Neto, Helena Sarmento. 595-598 [doi]
• Dynamic query switching for complex event processing on FPGAsMasamichi Takagi, Takashi Takenaka, Hiroaki Inoue. 599-602 [doi]
• Dual-core motion estimation processorJoaquín Olivares, José M. Palomares. 603-606 [doi]
• On the automatic integration of hardware accelerators into FPGA-based embedded systemsChristian Pilato, Andrea Cazzaniga, Gianluca Durelli, Andrés Otero, Donatella Sciuto, Marco D. Santambrogio. 607-610 [doi]
• Design of a novel Quantum-dot Cellular Automata Field Programmable Gate ArrayHemant Balijepalli, Mohammed Y. Niamat. 611-614 [doi]
• A predictive delay fault avoidance scheme for coarse-grained reconfigurable architectureToshihiro Kameda, Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. 615-618 [doi]
• DWARV 2.0: A CoSy-based C-to-VHDL hardware compilerRazvan Nane, Vlad Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova, Koen Bertels. 619-622 [doi]
• Low area memory-free FPGA implementation of the AES algorithmJunfeng Chu, Mohammed Benaissa. 623-626 [doi]
• An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfigurationHanaa M. Hussain, Khaled Benkrid, Chuan Hong, Huseyin Seker. 627-630 [doi]
• Fast digital rendering for special effectsSam Collinson, John Morris. 631-634 [doi]
• Design and utilization of an FPGA cluster to implement a Digital Wireless Channel EmulatorScott Buscemi, Ron Sass. 635-638 [doi]
• Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAsKazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano. 639-642 [doi]
• A new self-adapting architecture for feature detectionPaulo Da Cunha Possa, Sidi Ahmed Mahmoudi, Naim Harb, Carlos Valderrama. 643-646 [doi]
• Custom instructions with local memory elements without expensive DMA transfersAlok Prakash, Christopher T. Clarke, Thambipillai Srikanthan. 647-650 [doi]
• Dual MicroBlaze rekeying processor for group key managementJosé M. Granado Criado, Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido. 651-654 [doi]
• Lightweight reconfiguration security services for AXI-based MPSoCsPascal Cotret, Guy Gogniat, Jean-Philippe Diguet, Jérémie Crenne. 655-658 [doi]
• Examination of the concept of a row-column separated median filterDi Wang, Christopher T. Clarke, A. N. Evans. 659-662 [doi]
• On reconfigurable fabrics and generic side-channel countermeasuresRobert Beat, Philipp Grabher, Daniel Page, Stefan Tillich, Marcin Wójcik. 663-666 [doi]
• Hardware implementation of stereo correspondence algorithm for the ExoMars missionGeorge Lentaris, Dionysios Diamantopoulos, Kostas Siozios, Dimitrios Soudris, Marcos Avilés Rodrigálvarez. 667-670 [doi]
• Design space exploration for automatically generated cryptographic hardware using functional languagesDavy Wolfs, Kris Aerts, Nele Mentens. 671-674 [doi]
• Fast and accurate Single Bit Error injection into SRAM Based FPGAsUli Kretzschmar, Armando Astarloa, Jaime Jimenez, Mikel Garay, Javier Del Ser. 675-678 [doi]
• 2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable ArchitectureFrançois Philipp, Manfred Glesner. 679-682 [doi]
• Design and implementation of fault-tolerant soft processors on FPGAsChuan Hong, Khaled Benkrid, Xabier Iturbe, Ali Ebrahim. 683-686 [doi]
• Towards GCC-based automatic soft-core customizationGerald Hempel, Christian Hochberger, Michael Raitza. 687-690 [doi]
• An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminalsShadi Traboulsi, Wenlong Zhang, David Szczesny, Anas Showk, Attila Bilgic. 691-694 [doi]
• Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGAGordon Inggs, David Thomas, Simon Winberg. 695-698 [doi]
• ITester: A FPGA based high performance traffic replay toolFuxing Zhang, Yingke Xie, Junjie Liu, Layong Luo, Qingsong Ning, Xiaolong Wu. 699-702 [doi]
• Modeling and synthesis of a Dynamic and Partial Reconfiguration controllerSébastien Guillet, Florent de Lamotte, Nicolas Le Griguer, Éric Rutten, Jean-Philippe Diguet, Guy Gogniat. 703-706 [doi]
• An open-source design and validation platform for reconfigurable systemsAlessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio. 707-710 [doi]
• Floating point HOG implementation for real-time multiple object detectionMateusz Komorkiewicz, Maciej Kluczewski, Marek Gorgon. 711-714 [doi]
• Runtime reconfigurable DSP unit using one's complement and Minimum Signed DigitTravis Manderson, Laurence Turner. 715-718 [doi]
• A high performance and low energy intra prediction hardware for High Efficiency Video CodingErcan Kalali, Yusuf Adibelli, Ilker Hamzaoglu. 719-722 [doi]
• High-level linear projection circuit design optimization framework for FPGAs under over-clockingRui Policarpo Duarte, Christos-Savvas Bouganis. 723-726 [doi]
• Evaluating the efficiency of DSP Block synthesis inference from flow graphsBajaj Ronak, Suhaib A. Fahmy. 727-730 [doi]
• System#: High-level synthesis of physical simulations for FPGA-based real-time executionChristian Köllner, Nico Adler, Klaus D. Müller-Glaser. 731-734 [doi]
• Bil: A tool-chain for bitstream reverse-engineeringFlorian Benz, André Seffrin, Sorin A. Huss. 735-738 [doi]
• A region merging approach for image segmentation on FPGADang Ba Khac Trieu, Tsutomu Maruyama. 739-742 [doi]
• On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faultsPetr Pfeifer, Zdenek Plíva. 743-746 [doi]
• Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGASMaria Kalenderi, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Charalampos Manifavas. 747-753 [doi]