Table of Contents

• Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGAAnh Tuan Hoang, Takeshi Fujino. 1-10 [doi]
• Speedy FPGA-based packet classifiers with low on-chip memory requirementsChih-Hsun Chou, Fong Pong, Nian-Feng Tzeng. 11-20 [doi]
• A real-time stereo vision system using a tree-structured dynamic programming on FPGAMinxi Jin, Tsutomu Maruyama. 21-24 [doi]
• Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementationScott Bailie, Miriam Leeser. 25-28 [doi]
• X-ORCA: FPGA-based wireless localization in the sub-millimeter rangeMatthias Hinkfoth, Enrico Heinrich, Sebastian Vorköper, Volker Kühn, Ralf Salomon. 29-32 [doi]
• Communication visualization for bottleneck detection of high-level synthesis applicationsJohn Curreri, Greg Stitt, Alan D. George. 33-36 [doi]
• CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAsMichael Papamichael, James C. Hoe. 37-46 [doi]
• A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applicationsJeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt. 47-56 [doi]
• A mixed precision Monte Carlo methodology for reconfigurable accelerator systemsGary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas. 57-66 [doi]
• Saturating the transceiver bandwidth: switch fabric design on FPGAsZefu Dai, Jianwen Zhu. 67-76 [doi]
• The VTR project: architecture and CAD for FPGAs from verilog to routingJonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson. 77-86 [doi]
• Compiling high throughput network processorsMaysam Lavasani, Larry Dennison, Derek Chiou. 87-96 [doi]
• Limit study of energy & delay benefits of component-specific routingNikil Mehta, Raphael Rubin, André DeHon. 97-106 [doi]
• Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and powerWarren Wai-Kit Shum, Jason Helge Anderson. 107-110 [doi]
• Impact of FPGA architecture on resource sharing in high-level synthesisStefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski. 111-114 [doi]
• A fast discrete placement algorithm for FPGAsQinghong Wu, Kenneth S. McElvain. 115-118 [doi]
• Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter conesHadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne. 119-128 [doi]
• Securing netlist-level FPGA design through exploiting process variation and degradationJason Xin Zheng, Miodrag Potkonjak. 129-138 [doi]
• Prototype and evaluation of the CoRAM memory architecture for FPGA-based computingEric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai. 139-142 [doi]
• A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstructionWendi Wang, Bo Duan, Wen Tang, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun. 143-152 [doi]
• A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulationSameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno. 153-162 [doi]
• FPGA-accelerated 3D reconstruction using compressive sensingJianwen Chen, Jason Cong, Ming Yan, Yi Zou. 163-166 [doi]
• Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulationHaoran Li, Youn Sung Park, Zhengya Zhang. 167-170 [doi]
• Reliability of a softcore processor in a commercial SRAM-based FPGANathaniel H. Rollins, Michael J. Wirthlin. 171-174 [doi]
• Leveraging latency-insensitivity to ease multiple FPGA designKermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer. 175-184 [doi]
• A scalable approach for automated precision analysisDavid Boland, George A. Constantinides. 185-194 [doi]
• Optimizing SDRAM bandwidth for custom FPGA loop acceleratorsSamuel Bayliss, George A. Constantinides. 195-204 [doi]
• VirtualRC: a virtual FPGA platform for applications and tools portabilityRobert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam. 205-208 [doi]
• Multi-ported memories for FPGAs via XORCharles Eric LaForest, Ming G. Liu, Emma Rae Rapati, J. Gregory Steffan. 209-218 [doi]
• OCTAVO: an FPGA-centric processor familyCharles Eric LaForest, John Gregory Steffan. 219-228 [doi]
• Accelerator compiler for the VENICE vector processorZhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux. 229-232 [doi]
• FCache: a system for cache coherent processing on FPGAsVincent Mirian, Paul Chow. 233-236 [doi]
• A lean FPGA soft processor built using a DSP blockHui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell, Chidamber Kulkarni. 237-240 [doi]
• Functionally verifying state saving and restoration in dynamically reconfigurable systemsLingkan Gong, Oliver Diessel. 241-244 [doi]
• A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAsAssem A. M. Bsoul, Steven J. E. Wilton. 245-254 [doi]
• Reducing the cost of floating-point mantissa alignment and normalization in FPGAsYehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk. 255-264 [doi]
• Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only)Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani. 265 [doi]
• Accelerating short read mapping on an FPGA (abstract only)Yupeng Chen, Bertil Schmidt, Douglas L. Maskell. 265 [doi]
• The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only)Mei Wen, Nan Wu 0003, Qianming Yang, Chunyuan Zhang, Liang Zhao. 265 [doi]
• EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only)Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings. 266 [doi]
• A field programmable array core for image processing (abstract only)Declan Walsh, Piotr Dudek. 266 [doi]
• Adaptive FPGA-based robotics state machine architecture derived with genetic algorithms (abstract only)Jesus Savage, Rodrigo Savage, Marco Morales-Aguirre, Ángel Fernando Kuri Morales. 267 [doi]
• Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only)André Seffrin, Sorin A. Huss. 267 [doi]
• A novel full coverage test method for CLBs in FPGA (abstract only)Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai. 267 [doi]
• Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only)Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang. 268 [doi]
• FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)Jason Cong, Bingjun Xiao. 268 [doi]
• Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)Wei Ting Loke, Yajun Ha. 268 [doi]
• Efficient in-system RTL verification and debugging using FPGAs (abstract only)Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad. 269 [doi]
• OpenCL memory infrastructure for FPGAs (abstract only)S. Alexander Chin, Paul Chow. 269-270 [doi]
• Parallel FPGA placement based on individual LUT placement (abstract only)Chris C. Wang, Guy G. F. Lemieux. 269 [doi]
• Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only)Robin Panda, Scott Hauck. 269 [doi]
• Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only)Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So. 270 [doi]
• Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only)Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe. 271 [doi]
• Post-silicon debugging targeting electrical errors with patchable controllers (abstract only)Masahiro Fujita, Hiroaki Yoshida. 271 [doi]
• Early timing estimation for system-level design using FPGAs (abstract only)Hugo A. Andrade, Arkadeb Ghosal, Rhishikesh Limaye, Sadia Malik, Newton Petersen, Kaushik Ravindran, Trung N. Tran, Guoqiang Wang, Guang Yang. 271 [doi]
• Scalable architecture for 135 GBPS IPv6 lookup on FPGA (abstract only)Yi-Hua E. Yang, Oguzhan Erdem, Viktor K. Prasanna. 272 [doi]