Abstract is missing.
- Welcome from the general chairMatthew R. Guthaus. [doi]
- Design of a neural stimulator system with closed-loop charge cancellationLe Zheng, Sangho Shin, Sung-Mo Steve Kang. 1-6 [doi]
- Force-Directed List Scheduling for Digital Microfluidic BiochipsKenneth O'Neal, Daniel Grissom, Philip Brisk. 7-11 [doi]
- Low noise front-end amplifier design for medical ultrasound imaging applicationsSurya Sharma, Trond Ytterdal. 12-17 [doi]
- An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidthMingyang Zhu, Jinho Lee, Kiyoung Choi. 18-23 [doi]
- ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnectionsAnelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro. 24-29 [doi]
- 3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memoryGiulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini. 30-35 [doi]
- Safety oriented automotive MCU power managementStefano Pietri, Chris Dao, Juxiang Ren, Jehoda Refaeli, Alfredo Olmos. 36-40 [doi]
- CMOS implementation of static threshold gates with hysteresis: A new approachFarhad Alibeygi Parsan, Scott C. Smith. 41-45 [doi]
- th-order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOSSohail Asghar, Rocio del Río, José Manuel de la Rosa. 47-52 [doi]
- A novel double floating-gate unified memory deviceNeil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon. 53-58 [doi]
- Harmonic resonant clockingH. Blake Skinner, Xuchu Hu, Matthew R. Guthaus. 59-64 [doi]
- A multimode decision-directed channel estimation ASIC for MIMO-OFDMAndreas Minwegen, Dominik Auras, Gerd Ascheid. 65-70 [doi]
- Turbo decoder design for high code ratesChristian Benkeser, Christoph Roth, Qiuting Huang. 71-75 [doi]
- A novel elementary memristive systemFernando Corinto, Alon Ascoli, Marco Gilli. 76-81 [doi]
- Mapping of image and network processing tasks on high-throughput CMOL FPGA circuitsAdvait Madhavan, Dmitri B. Strukov. 82-87 [doi]
- Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devicesLigang Gao, Fabien Alibart, Dmitri B. Strukov. 88-93 [doi]
- GMS: Generic memristive structure for non-volatile FPGAsPierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli. 94-98 [doi]
- Arithmetic encoding for memristive multi-bit storageRavi Patel, Eby G. Friedman. 99-104 [doi]
- A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOSPierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak. 105-110 [doi]
- Cost-effective smart memory implementation for parallel backprojection in computed tomographyQiuling Zhu, Larry Pileggi, Franz Franchetti. 111-116 [doi]
- A low-cost and high efficiency entropy encoder architecture for H.264/AVCCristiano Thiele, Bruno Boessio Vizzotto, André L. M. Martinez, Vagner Santos Da Rosa, Sergio Bampi. 117-122 [doi]
- 100 Gbit/s authenticated encryption based on quantum key distributionMichael Muehlberghuber, Christoph Keller, Norbert Felber, Christian Pendl. 123-128 [doi]
- On the optimized generation of Software-Based Self-Test programs for VLIW processorsDavide Sabena, Matteo Sonza Reorda, Luca Sterpone. 129-134 [doi]
- Equivalence checking of nonlinear analog circuits for hierarchical AMS System VerificationSebastian Steinhorst, Lars Hedrich. 135-140 [doi]
- Interval arithmetic based input vector control for RTL subthreshold leakage minimizationShilpa Pendyala, Srinivas Katkoori. 141-146 [doi]
- Dynamic power management for multicores: Case study using the intel SCCRadu David, Paul Bogdan, Radu Marculescu. 147-152 [doi]
- A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architectureZhibin Xiao, Bevan M. Baas. 153-158 [doi]
- TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensingJeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg. 159-164 [doi]
- A physical design study of fabscalar-generated superscalar coresNiket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg. 165-170 [doi]
- A scalable model based RTL framework zamiaCAD for static analysisAnton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov. 171-176 [doi]
- A digital microfluidic biochip synthesis frameworkDaniel Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao, Philip Brisk. 177-182 [doi]
- ArchFP: Rapid prototyping of pre-RTL floorplansGregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer. 183-188 [doi]
- Reliability enhancement of power gating transistor under time dependent dielectric breakdownHamid Mahmoodi. 189-194 [doi]
- Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memoriesMuhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba. 195-200 [doi]
- Suppression of on-chip power supply noise generated by a 64-bit static logic ALU blockTasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev. 201-206 [doi]
- Dynamic voltage scaling for SEU-tolerance in low-power memoriesSeokjoong Kim, Matthew R. Guthaus. 207-212 [doi]
- Methodology for early estimation of hierarchical routing resources in 3D FPGAsKrishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki Murakami. 213-218 [doi]
- A single-VDD ultra-low energy sub-threshold FPGARajsaktish Sankaranarayanan, Matthew R. Guthaus. 219-224 [doi]
- Evaluation of fault tolerant technique based on homogeneous FPGA architectureYuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 225-230 [doi]
- Load-aware stochastic feedback control for DVFS with tight performance guaranteeBin Wu, Peng Li. 231-236 [doi]
- Aging-aware caches with graceful degradation of performanceHaroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii. 237-242 [doi]
- Topology-aware reliability optimization for multiprocessor systemsJie Meng, Fulya Kaplan, Mingyu Hsieh, Ayse Kivilcim Coskun. 243-246 [doi]
- Trinocular disparity processor using a hierarchic classification structureAndy Motten, Luc Claesen, Yun Pan. 247-250 [doi]
- Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4Anupam Chattopadhyay, Goutam Paul. 251-254 [doi]
- Reliability study on system memories of an iterative MIMO-BICM systemChristina Gimmler-Dumont, Christian Brehm, Norbert Wehn. 255-258 [doi]
- A new reliability evaluation methodology and its application to network-on-chip routersHamed Sajjadi Kia, Cristinel Ababei. 259-262 [doi]
- Cost-effective TSV redundancy configurationJongpil Jung, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, Chong-Min Kyung. 263-266 [doi]
- The impact of synchronization in message passing while scaling multi-core MPSoC systemsVictor Frederico Silva, Cantidio de Oliveira Fontes, Flávio Rech Wagner. 267-270 [doi]
- FPGA power reduction by guarded evaluation considering physical informationChirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson. 271-274 [doi]
- A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nmJaspal Singh Shah, David Nairn, Manoj Sachdev. 275-278 [doi]
- Successive interference cancellation for 3G downlink: Algorithm and VLSI architectureSandro Belfanti, Christian Benkeser, Karim Badawi, Qiuting Huang, Andreas Burg. 279-282 [doi]
- A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memoryKyungsu Kang, Luca Benini, Giovanni De Micheli. 283-286 [doi]
- Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memoryAvijit Dutta. 287-290 [doi]
- An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependenceTakeshi Matsumoto, Shohei Ono, Masahiro Fujita. 291-294 [doi]
- Impact of technology scaling on performance of domino logic in nano-scale CMOSAbhishek Guar, Hamid Mahmoodi. 295-298 [doi]
- ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processorsHamed Tabkhi, Gunar Schirner. 299-302 [doi]
- A complete over-current/short-circuit protection system for Low-Drop Out regulatorsIlias Pappas, Vasilios Kalenteridis, Stylianos Siskos, Spiridon Vlassis. 303-306 [doi]
- Low power SoCs with resonant dynamic logic using inductors for energy recoveryIgnatius Bezzam, Shoba Krishnan, Chakravarthy Mathiazhagan. 307-310 [doi]
- Efficient adaptive switch design for charge pumps in micro-scale energy harvestingK. T. Hafeez, Ashudeb Dutta, Shiv Govind Singh. 311-314 [doi]