Table of Contents

• ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General AbstractionsXiuping Cui, Size Zheng 0001, Tianyu Jia, Le Ye, Yun Liang 0001. 1-9 [doi]
• Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation SystemRuiyao Pu, Yiwei Sun, Pei-Hsin Ho, Fan Yang 0001, Li Shang, Xuan Zeng 0001. 1-9 [doi]
• Local Layout Effect-Aware Static Timing Analysis by use of a New Sensitivity-Based LibraryJuyeon Kim, ChangHo Han, Cheoljun Bae, Yoobeom Kim, Jae-Hoon Kim, Hyungjung Seo. 1-6 [doi]
• BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer LearningChuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo. 1-9 [doi]
• Rapid-INR: Storage Efficient CPU-Free DNN Training Using Implicit Neural RepresentationHanqiu Chen, Hang Yang, Stephen B. R. Fitzmeyer, Cong Hao. 1-9 [doi]
• Effective and Efficient Qubit MapperHao Fu, Mingzheng Zhu, Jun Wu, Wei Xie, Zhaofeng Su, Xiang-Yang Li. 1-9 [doi]
• Accelerating Exact Combinatorial Optimization via RL-based Initialization - A Case Study in SchedulingJiaqi Yin, Cunxi Yu. 1-9 [doi]
• Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean OperationsDavid Clarino, Naoya Asada, Shigeru Yamashita. 1-8 [doi]
• MirrorNet: A TEE-Friendly Framework for Secure On-Device DNN InferenceZiyu Liu, Yukui Luo, Shijin Duan, Tong Zhou 0002, Xiaolin Xu. 1-9 [doi]
• INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation ProcessingStefan Abi-Karam, Rishov Sarkar, Dejia Xu, Zhiwen Fan, Zhangyang Wang, Cong Hao. 1-9 [doi]
• PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based SignaturesHuifeng Zhu, Weidong Cao, Xuan Zhang. 1-8 [doi]
• An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography ModelingMingjie Liu, Haoyu Yang, Brucek Khailany, Haoxing Ren. 1-9 [doi]
• Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network InferenceTianshi Xu, Meng Li 0004, Runsheng Wang, Ru Huang. 1-9 [doi]
• Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function SynthesisBoyu Long, Libo Shen, Xiaoyu Zhang 0009, Yinhe Han 0001, Xian-He Sun, Xiaoming Chen. 1-9 [doi]
• Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial AcceleratorsXiaochen Hao, Zijian Ding, Jieming Yin, Yuan Wang 0001, Yun Liang 0001. 1-9 [doi]
• VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN AcceleratorJe-Woo Jang, Thai-Hoang Nguyen, Joon-Sung Yang. 1-9 [doi]
• Clock Aware Low Power PlacementJinghao Ding, Linhao Lu, Zhaoqi Fu, Jie Ma, Mengshi Gong, Yuanrui Qi, Wenxin Yu. 1-8 [doi]
• Exploration and Exploitation of Hidden PMU EventsYihao Yang, Pengfei Qiu, Chunlu Wang, Yu Jin, Qiang Gao, Xiaoyong Li 0003, Dongsheng Wang 0002, Gang Qu 0001. 1-9 [doi]
• Invited Paper: Overview of 2023 CAD Contest at ICCADTakashi Sato, Chun-Yao Wang, Yu-Guang Chen, Tsung-Wei Huang. 1-6 [doi]
• 3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN AcceleratorsGauthaman Murali, Aditya Iyer, Navneeth Ravichandran, Sung Kyu Lim. 1-9 [doi]
• DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAsErjing Luo, Haitong Huang, Cheng Liu 0008, Guoyu Li, Bing Yang, Ying Wang 0001, Huawei Li, Xiaowei Li 0001. 1-9 [doi]
• RONet: Scaling GPU System with Silicon Photonic ChipletChengeng Li, Fan Jiang, Shixi Chen, Xianbin Li, Yinyi Liu, Lin Chen, Xiao Li, Jiang Xu 0001. 1-9 [doi]
• Invited Paper: Towards the Efficiency, Heterogeneity, and Robustness of Edge AIBokyung Kim, Zhixu Du, Jingwei Sun 0002, Yiran Chen 0001. 1-7 [doi]
• Data Recomputation for Multithreaded ApplicationsGulsum Gudukbay Akbulut, Mahmut T. Kandemir, Mustafa Karaköy, Wonil Choi. 1-9 [doi]
• Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code GenerationMingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren. 1-8 [doi]
• Power Distribution Network Optimization Using HLA-GCN for Routability EnhancementYounggwang Jung, Daijoon Hyun, Soyoon Choi, Youngsoo Shin. 1-8 [doi]
• Invited Paper: A Scalable Hardware/Software Co-Design Approach for Efficient Polynomial MultiplicationLóránt Meszlényi, Elif Bilge Kavun, Irem Keskinkurt Paksoy, Avesha Khalid, Tolga Yalçin. 1-5 [doi]
• Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level SynthesisAlexander El-Kady, Apostolos P. Fournaris, Vassilis Paliouras. 1-7 [doi]
• Risk-Aware and Explainable Framework for Ensuring Guaranteed Coverage in Evolving Hardware Trojan DetectionRahul Vishwakarma, Amin Rezaei 0001. 1-9 [doi]
• Invited Paper: Introduction to Hybrid Quantum-Classical Programming Using C++ Quantum ExtensionXin-Chuan Wu, Shavindra P. Premaratne, Kevin Rasch. 1-6 [doi]
• Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion PredictionSu Zheng, Lancheng Zou, Peng Xu, Siting Liu 0002, Bei Yu 0001, Martin D. F. Wong. 1-9 [doi]
• Invited Paper: Accelerating Next-G Wireless Communications with FPGA-Based AI AcceleratorsChunxiao Lin, Muhammad Farhan Azmine, Yang Yi. 1-8 [doi]
• Invited Paper: 2023 ICCAD CAD Contest Problem C: Static IR Drop Estimation Using Machine LearningGana Surya Prakash Kadagala, Vidya A. Chhabria. 1-5 [doi]
• Full State Quantum Circuit Simulation Beyond Memory LimitYilun Zhao 0002, Yu Chen, He Li, Ying Wang, Kaiyan Chang, Bingmeng Wang, Bing Li, Yinhe Han 0001. 1-9 [doi]
• Risk Propagation Based Vector Profiling for High Coverage Dynamic IR-Drop AnalysisYihan Wen, Juan Li, Xiaoyi Wang. 1-8 [doi]
• PostPINN-EM: Fast Post-Voiding Electromigration Analysis Using Two-Stage Physics-Informed Neural NetworksSubed Lamichhane, Wentian Jin, Liang Chen 0025, Mohammadamir Kavousi, Sheldon X.-D. Tan. 1-9 [doi]
• LFPS: Learned Formal Proof Strengthening for Efficient Hardware VerificationMinwoo Kang, Azade Nova, Eshan Singh, Geetheeka Sharron Bathini, Yuriy Viktorov. 1-9 [doi]
• An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream SamplingChangchun Zhou, Yuzhe Fu, Min Liu, Siyuan Qiu, Ge Li, Yifan He, Hailong Jiao. 1-9 [doi]
• Memory-aware Scheduling for Complex Wired Networks with Iterative Graph OptimizationShuzhang Zhong, Meng Li 0004, Yun Liang 0001, Runsheng Wang, Ru Huang. 1-9 [doi]
• Exact Logic Synthesis for Reversible Quantum-Flux-Parametron LogicRongliang Fu, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho. 1-9 [doi]
• GraPhSyM: Graph Physical Synthesis ModelAhmed Agiza, Rajarshi Roy 0003, Teodor-Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro. 1-9 [doi]
• RNA-ViT: Reduced-Dimension Approximate Normalized Attention Vision Transformers for Latency Efficient Private InferenceDake Chen, Yuke Zhang, Souvik Kundu 0002, Chenghao Li, Peter A. Beerel. 1-9 [doi]
• Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean MatchingChung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo. 1-4 [doi]
• Fast Exact NPN Classification with Influence-Aided Canonical FormYonghe Zhang, Liwei Ni, Jiaxi Zhang 0001, Guojie Luo, Huawei Li 0001, Shenggen Zheng. 1-9 [doi]
• One-Dimensional Deep Image Prior for Curve Fitting of S-Parameters from Electromagnetic SolversSriram Ravula, Varun Gorti, Bo Deng, Swagato Chakraborty, James Pingenot, Bhyrav Mutnury, Douglas Wallace, Douglas Winterberg, Adam R. Klivans, Alexandros G. Dimakis. 1-9 [doi]
• DOMINO: Domain-Invariant Hyperdimensional Classification for Multi-Sensor Time Series DataJunyao Wang, Luke Chen, Mohammad Abdullah Al Faruque. 1-9 [doi]
• Single-Qubit Gates Matter for Optimising Quantum Circuit Depth in Qubit MappingSanjiang Li, Ky Dan Nguyen, Zachary Clare, Yuan Feng 0001. 1-9 [doi]
• PSOFuzz: Fuzzing Processors with Particle Swarm OptimizationChen Chen, Vasudev Gohil, Rahul Kande, Ahmad-Reza Sadeghi, Jeyavijayan Rajendran. 1-9 [doi]
• Floorplanning for Embedded Multi-Die Interconnect Bridge PackagesChung-Chia Lee, Yao-Wen Chang. 1-8 [doi]
• AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree SearchZehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, Bei Yu 0001. 1-9 [doi]
• Accelerating Polynomial Modular Multiplication with Crossbar-Based Compute-in-MemoryMengyuan Li, Haoran Geng, Michael T. Niemier, Xiaobo Sharon Hu. 1-9 [doi]
• SOLE: Hardware-Software Co-design of Softmax and LayerNorm for Efficient Transformer InferenceWenxun Wang, Shuchang Zhou 0001, Wenyu Sun, Peiqin Sun, Yongpan Liu. 1-9 [doi]
• Towards Timing-Driven Routing: An Efficient Learning Based Geometric ApproachLiying Yang, Guowei Sun, Hu Ding. 1-9 [doi]
• SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload BalanceSanjay Gandham, Lingxiang Yin, Hao Zheng 0005, Mingjie Lin. 1-9 [doi]
• Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline FloorplanningFuxing Huang, Duanxiang Liu, Xingquan Li, Bei Yu 0001, Wenxing Zhu. 1-9 [doi]
• VecPAC: A Vectorizable and Precision-Aware CGRACheng Tan 0002, Deepak Patil, Antonino Tumeo, Gabriel Weisz, Steven K. Reinhardt, Jeff Zhang 0001. 1-9 [doi]
• PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning SolutionsQijun Zhang, Shiyu Li, Guanglei Zhou, Jingyu Pan, Chen-Chia Chang, Yiran Chen 0001, Zhiyao Xie. 1-9 [doi]
• Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution NetworksXi Xie, Hongwu Peng, Md Amit Hasan, Shaoyi Huang, Jiahui Zhao, Haowen Fang, Wei Zhang, Tong Geng, Omer Khan, Caiwen Ding. 1-9 [doi]
• Fast Full-Chip Parametric Thermal Analysis Based on Enhanced Physics Enforced Neural NetworksLiang Chen 0025, Jincong Lu, Wentian Jin, Sheldon X.-D. Tan. 1-8 [doi]
• Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-Level Sparsity via Mixture-of-ExpertsRishov Sarkar, Hanxue Liang, Zhiwen Fan, Zhangyang Wang, Cong Hao. 1-9 [doi]
• A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic ComputingWei-Lun Chen, Fang-Yi Gu, Ing-Chao Lin, Grace Li Zhang, Bing Li, Ulf Schlichtmann. 1-9 [doi]
• FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer NetworksYueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Yu 0010, Kun Wang 0005. 1-9 [doi]
• Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTLTobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz. 1-9 [doi]
• Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD ResearchJinwook Jung, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Dooseok Yoon. 1-7 [doi]
• GRAFT: Graph-Assisted Reinforcement Learning for Automated SSD Firmware TestingYoon Hyeok Lee, Youngmin Oh, Gyohun Jeong, Mingyu Pi, Hyukil Kwon, Hakyoung Lim, Eungchae Kim, Sunghee Lee, Bosun Hwang. 1-8 [doi]
• ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible InterconnectsLingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng 0005. 1-9 [doi]
• Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative StudyQiao Yu, Wengui Zhang, Jorge Cardoso 0001, Odej Kao. 1-9 [doi]
• Invited Paper: Solving Fine-Grained Static 3DIC Thermal with ML Thermal Solver Enhanced with Decay Curve CharacterizationHaiyang He, Norman Chang, Jie Yang 0023, Akhilesh Kumar, Wenbo Xia, Lang Lin, Rishikesh Ranade. 1-7 [doi]
• Systolic Array Placement on FPGAsHailiang Hu, Donghao Fang, Wuxi Li, Bo Yuan 0001, Jiang Hu. 1-9 [doi]
• Accurate Hybrid Delay Models for Dynamic Timing AnalysisArman Ferdowsi, Ulrich Schmid 0001, Josef Salzmann. 1-9 [doi]
• Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian NoiseZheyu Yan, Yifan Qin, Wujie Wen, Xiaobo Sharon Hu, Yiyu Shi 0001. 1-9 [doi]
• IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB BottleneckShashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic. 1-9 [doi]
• Fast and Fair Medical AI on the Edge Through Neural Architecture Search for Hybrid Vision ModelsChangdi Yang, Yi-sheng, Peiyan Dong, Zhenglun Kong, Yanyu Li, Pinrui Yu, Lei Yang, Xue Lin, Yanzhi Wang. 1-9 [doi]
• Efficient Sampling and Grouping Acceleration for Point Cloud Deep Learning via Single Coordinate ComparisonHyunsung Yoon, Jae-Joon Kim. 1-9 [doi]
• TRAIN: A Reinforcement Learning Based Timing-Aware Neural Inference on Intermittent SystemsShu-Ting Cheng, Wen Sheng Lim, Chia-Heng Tu, Yuan-Hao Chang 0001. 1-9 [doi]
• Automated Hardware Trojan Detection at LUT Using Explainable Graph Neural NetworksLingjuan Wu, Hao Su, Xuelin Zhang, Yu Tai, Han Li, Wei Hu 0008. 1-9 [doi]
• Optimal Layout Synthesis for Quantum Circuits as Classical PlanningIrfansha Shaik, Jaco van de Pol. 1-9 [doi]
• NearUni: Near-Unitary Training for Efficient Optical Neural NetworksAmro Eldebiky, Bing Li 0005, Grace Li Zhang. 1-8 [doi]
• Invited Paper: 2023 ICCAD CAD Contest Problem B: 3D Placement with MacrosKai-Shun Hu, Hao-Yu Chi, I-Jye Lin, Yi Hsuan Wu, Wei-Hsu Chen, Yi-Ting Hsieh. 1-6 [doi]
• FuNToM: Functional Modeling of RF Circuits Using a Neural Network Assisted Two-Port Analysis MethodMorteza Fayazi, Morteza Tavakoli Taba, Amirata Tabatabavakili, Ehsan Afshari, Ronald G. Dreslinski. 1-8 [doi]
• Routability Prediction and Optimization Using Explainable AISeongHyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang. 1-8 [doi]
• Fast and Scalable Gate-Level Simulation in Massively Parallel SystemsHaichuan Hu, Zichen Xu 0001, Yuhao Wang, Fangming Liu. 1-9 [doi]
• MiniTNtk: An Exact Synthesis-based Method for Minimizing Transistor NetworkWeihua Xiao, Shanshan Han, Yue Yang, Shaoze Yang, Cheng Zheng, Jingsong Chen, Tingyuan Liang, Lei Li, Weikang Qian. 1-9 [doi]
• Efficient Formal Verification and Debugging of Arithmetic Divider CircuitsJiteshri Dasari, Maciej J. Ciesielski. 1-9 [doi]
• HidFix: Efficient Mitigation of Cache-Based Spectre Attacks Through Hidden RollbacksArash Pashrashid, Ali Hajiabadi, Trevor E. Carlson. 1-9 [doi]
• EMSim+: Accelerating Electromagnetic Security Evaluation with Generative Adversarial NetworkYa Gao, Haocheng Ma, Jindi Kong, Jiaji He, Yiqiang Zhao, Yier Jin. 1-8 [doi]
• MOC: Multi-Objective Mobile CPU-GPU Co-Optimization for Power-Efficient DNN InferenceYushu Wu, Yifan Gong 0004, Zheng Zhan 0001, Geng Yuan, Yanyu Li, Qi Wang, Chao Wu, Yanzhi Wang. 1-10 [doi]
• GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language ModelsYonggan Fu, Yongan Zhang, Zhongzhi Yu, Sixu Li, Zhifan Ye, Chaojian Li, Cheng Wan, Yingyan Celine Lin. 1-9 [doi]
• Invited Paper: Hyperdimensional Computing for Resilient Edge LearningHamza Errahmouni Barkam, SungHeon Eavn Jeon, Sanggeon Yun, Calvin Yeung, Zhuowen Zou, Xun Jiao, Narayan Srinivasa, Mohsen Imani. 1-8 [doi]
• Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive ApplicationsMuhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha 0001, Hao Zheng 0005, Rickard Ewetz. 1-9 [doi]
• Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary ComputingAlireza Khataei, Kia Bazargan. 1-7 [doi]
• Verification of Flow-Based Computing Systems Using Bounded Model CheckingSven Thijssen, Suraj Singireddy, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Rickard Ewetz. 1-9 [doi]
• Towards Effective Training of Robust Spiking Recurrent Neural Networks Under General Input Noise via Provable AnalysisWendong Zheng, Yu Zhou, Gang Chen 0023, Zonghua Gu 0001, Kai Huang. 1-9 [doi]
• PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAMAnjiang Wei, Akash Levy, Pu Yi, Robert M. Radway, Priyanka Raina, Subhasish Mitra, Sara Achour. 1-9 [doi]
• DiviML: A Module-based Heuristic for Mapping Neural Networks onto Heterogeneous PlatformsYassine Ghannane, Mohamed S. Abdelfattah. 1-9 [doi]
• Invited Paper: Towards the Imagenets of ML4EDAAnimesh Basak Chowdhury, Shailja Thakur, Hammond Pearce, Ramesh Karri, Siddharth Garg. 1-7 [doi]
• MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance OptimizationHanyu Wang, Carmine Rizzi, Lana Josipovic. 1-9 [doi]
• SpOctA: A 3D Sparse Convolution Accelerator with Octree-Encoding-Based Map Search and Inherent Sparsity-Aware ProcessingDongxu Lyu, Zhenyu Li, Yuzhou Chen, Jinming Zhang, Ningyi Xu, Guanghui He. 1-9 [doi]
• Reflections on Trusting TrustHUBChristian Krieg. 1-9 [doi]
• Integrating Exact Simulation into Sweeping for Datapath Combinational Equivalence CheckingZhihan Chen, Xindi Zhang, Yuhang Qian, Qiang Xu 0001, Shaowei Cai 0001. 1-9 [doi]
• Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural NetworksAhmet Faruk Budak, Keren Zhu 0001, David Z. Pan. 1-8 [doi]
• READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern ReductionZuodong Zhang, Renjie Wei, Meng Li 0004, Yibo Lin, Runsheng Wang, Ru Huang. 1-9 [doi]
• PP-Transformer: Enable Efficient Deployment of Transformers Through Pattern PruningJialin Cao, Xuanda Lin, Manting Zhang, Kejia Shi, Jun Yu 0010, Kun Wang 0005. 1-9 [doi]
• Invited Paper: Heterogeneous Acceleration for Design Rule CheckingZhuolun He, Bei Yu 0001. 1-7 [doi]
• Hyperdimensional Computing as a Rescue for Efficient Privacy-Preserving Machine Learning-as-a-ServiceJaewoo Park, Chenghao Quan, Hyungon Moon, Jongeun Lee. 1-8 [doi]
• $\mathcal{D}\mathsf{iCA}$: A Hardware-Software Co-Design for Differential Check-Pointing in Intermittently Powered DevicesAntonio Joia Neto, Adam Caulfield, Chistabelle Alvares, Ivan De Oliveira Nunes. 1-9 [doi]
• EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive SequencingPeiyu Wang, Anqi Lu, Xing Li, Junjie Ye, Lei Chen 0031, Mingxuan Yuan, Jianye Hao, Junchi Yan. 1-9 [doi]
• WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic CircuitsKuo-Wei Ho, Shao-Ting Chung, Tian-Fu Chen, Yu-Wei Fan, Che Cheng, Cheng-Han Liu, Jie-Hong R. Jiang. 1-9 [doi]
• Invited Paper: Learned In-Sensor Visual Computing: From Compression to EventificationYu Feng 0007, Tianrui Ma, Adith Boloor, Yuhao Zhu 0001, Xuan Zhang 0001. 1-9 [doi]
• SATformer: Transformer-Based UNSAT Core LearningZhengyuan Shi, Min Li 0019, Yi Liu, Sadaf Khan, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Qiang Xu 0001. 1-4 [doi]
• Side Channel-Assisted Inference Attacks on Machine Learning-Based ECG ClassificationJialin Liu 0006, Houman Homayoun, Chongzhou Fang, Ning Miao, Han Wang. 1-9 [doi]
• ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural NetworksKyungjun Min, Seongbin Kwon, Sung Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang. 1-9 [doi]
• LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-MemoryAyumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi. 1-9 [doi]
• An Anti-Removal-Attack Hardware Watermarking Method Based on Polymorphic GatesYongliang Chen, Xiaole Cui, Pengyuan Yang, Gang Qu 0001. 1-9 [doi]
• Multi-Product Optimization for 3D Heterogeneous Integration with D2W BondingZhen Zhuang, Kai-Yuan Chao, Bei Yu 0001, Tsung-Yi Ho, Martin D. F. Wong. 1-9 [doi]
• Invited Paper: The Inevitability of AI Infusion Into Design Closure and SignoffJiang Hu, Andrew B. Kahng. 1-7 [doi]
• Real-time Thermal Map Estimation for AMD Multi-Core CPUs Using TransformerJincong Lu, Jinwei Zhang, Sheldon X.-D. Tan. 1-7 [doi]
• Protection Against Physical Attacks Through Self-Destructive Polymorphic LatchAndrew Cannon, Tasnuva Farheen, Sourav Roy, Shahin Tajik, Domenic Forte. 1-9 [doi]
• Runtime Row/Column Activation Pruning for ReRAM-based Processing-in-Memory DNN AcceleratorsXikun Jiang, Zhaoyan Shen, Siqing Sun, Ping Yin, Zhiping Jia, Lei Ju 0001, Zhiyong Zhang, Dongxiao Yu. 1-9 [doi]
• KyberMat: Efficient Accelerator for Matrix-Vector Polynomial Multiplication in CRYSTALS-Kyber Scheme via NTT and Polyphase DecompositionWeihang Tan, Yingjie Lao, Keshab K. Parhi. 1-9 [doi]
• Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-FlopsSuwan Kim, Taewhan Kim. 1-9 [doi]
• FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic AcceleratorYinyi Liu, Bohan Hu, Zhenguo Liu, Peiyu Chen, Linfeng Du, Jiaqi Liu, Xianbin Li, Wei Zhang, Jiang Xu. 1-9 [doi]
• Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific ToolingChris Lavin, Eddie Hung. 1-7 [doi]
• A Transfer Learning Framework for High-Accurate Cross-Workload Design Space Exploration of CPUDuo Wang, Mingyu Yan, Yihan Teng, Dengke Han, Haoran Dang, Xiaochun Ye, Dongrui Fan. 1-9 [doi]
• Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer PerceptronsFlorentia Afentaki, Gurol Saglam, Argyris Kokkinis, Kostas Siozios, Georgios Zervakis 0001, Mehdi B. Tahoori. 1-9 [doi]
• A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology DesignsYan-Lin Chen, Wei-Che Tseng, Wei-Yao Kao, Yao-Wen Chang. 1-7 [doi]
• iPL-3D: A Novel Bilevel Programming Model for Die-to-Die PlacementXueyan Zhao, Shijian Chen, Yihang Qiu, Jiangkao Li, Zhipeng Huang 0009, Biwei Xie, Xingquan Li, Yungang Bao. 1-9 [doi]
• THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic ExecutionYuntao Wei, Xueyan Wang, Song Bian 0001, Weisheng Zhao, Yier Jin. 1-9 [doi]
• Robust GNN-Based Representation Learning for HLSAtefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong. 1-9 [doi]
• Invited Paper: Instruction Set Extensions for Post-Quantum CryptographyMarco Brohet, Felipe Valencia, Francesco Regazzoni 0001. 1-6 [doi]
• Analog or Digital In-Memory Computing? Benchmarking Through Quantitative ModelingJiacong Sun, Pouya Houshmand, Marian Verhelst. 1-9 [doi]
• Deep-Learning Model Extraction Through Software-Based Power Side-ChannelXiang Zhang, Aidong Adam Ding, Yunsi Fei. 1-9 [doi]
• Brain-Inspired Trustworthy Hyperdimensional Computing with Efficient Uncertainty QuantificationYang Ni, Hanning Chen, Prathyush Poduval, Zhuowen Zou, Pietro Mercati, Mohsen Imani. 1-9 [doi]
• HyperNode: An Efficient Node Classification Framework Using HyperDimensional ComputingHaomin Li, Fangxin Liu, Yichi Chen, Li Jiang 0002. 1-9 [doi]
• EDS-SLAM: An Energy-Efficient Accelerator for Real-Time Dense Stereo SLAM with Learned Feature MatchingQian Huang, Gaoxing Shang, Yu Zhang, Gang Chen 0023. 1-9 [doi]
• TSTC: Two-Level Sparsity Tensor Core Enabling both Algorithm Flexibility and Hardware EfficiencyJun Liu, Guohao Dai, Hao Xia, Lidong Guo, Xiangsheng Shi, Jiaming Xu, Huazhong Yang, Yu Wang. 1-9 [doi]
• Invited Paper: In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent RadarYang Sui, Minning Zhu, Lingyi Huang, Chung-Tse Michael Wu, Bo Yuan 0001. 1-9 [doi]
• EasySO: Exploration-enhanced Reinforcement Learning for Logic Synthesis Sequence Optimization and a Comprehensive RL EnvironmentJianyong Yuan, Peiyu Wang, Junjie Ye, Mingxuan Yuan, Jianye Hao, Junchi Yan. 1-9 [doi]
• SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?Andrija Neskovic, Saleh Mulhem, Alexander Treff, Rainer Buchty, Thomas Eisenbarth 0001, Mladen Berekovic. 1-8 [doi]
• Stronger Mixed-Size Placement Backbone Considering Second-Order InformationYifan Chen, Zaiwen Wen, Yun Liang 0001, Yibo Lin. 1-9 [doi]
• $\mathcal{P}\text{ARseL}$: Towards a Verified Root-of-Trust Over seL4Ivan De Oliveira Nunes, Seoyeon Hwang, Sashidhar Jakkamsetti, Norrathep Rattanavipanon, Gene Tsudik. 1-9 [doi]
• Klotski: DNN Model Orchestration Framework for Dataflow Architecture AcceleratorsChen Bai, Xuechao Wei, Youwei Zhuo, Yi Cai, Hongzhong Zheng, Bei Yu 0001, Yuan Xie 0001. 1-9 [doi]
• Delay-Matching Routing for Advanced PackagesChun-An Lee, Wen-Hao Liu, Gary Lin, Tsung-Yi Ho. 1-8 [doi]
• Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit OptimizationRongjian Liang, Anthony Agnesina, Geraldo Pradipta, Vidya A. Chhabria, Haoxing Ren. 1-6 [doi]
• CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital SignatureNaina Gupta 0001, Arpan Jati, Anupam Chattopadhyay. 1-7 [doi]
• Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM ConsiderationsDa Wei Huang, Ying-Jie Jiang, Shao-Yun Fang. 1-8 [doi]
• SEE-MCAM: Scalable Multi-Bit FeFET Content Addressable Memories for Energy Efficient Associative SearchShengxi Shou, Che-Kai Liu, Sanggeon Yun, Zishen Wan, Kai Ni 0004, Mohsen Imani, X. Sharon Hu, Jianyi Yang, Cheng Zhuo, Xunzhao Yin. 1-9 [doi]
• Kernel Shape Control for Row-Efficient Convolution on Processing-In-Memory ArraysJohnny Rhe, Kang Eun Jeon, Joochan Lee, Seongmoon Jeong, Jong Hwan Ko. 1-9 [doi]
• Automatic Kernel Generation for Large Language Models on Deep Learning AcceleratorsFuyu Wang, Minghua Shen. 1-9 [doi]
• EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and PruningXing Li, Lei Chen, Jiantang Zhang, Shuang Wen 0007, Weihua Sheng, Yu Huang, Mingxuan Yuan. 1-9 [doi]
• DASALS: Differentiable Architecture Search-Driven Approximate Logic SynthesisXuan Wang, Zheyu Yan, Chang Meng, Yiyu Shi 0001, Weikang Qian. 1-9 [doi]
• Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D IntegrationShubham Kumar, Yogesh Singh Chauhan, Hussam Amrouch. 1-6 [doi]
• MU-MIMO Detection Using Oscillator Ising MachinesShreesha Sreedhara, Jaijeet Roychowdhury, Joachim Wabnig, Pavan Koteshwar Srinath. 1-9 [doi]
• An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical DesignIsmail Bustany, Grigor Gasparyan, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang. 1-9 [doi]
• QPulseLib: Accelerating the Pulse Generation of Quantum Circuit with Reusable PatternsWuwei Tian, Xinghui Jia, Siwei Tan, Zixuan Song, Liqiang Lu, Jianwei Yin. 1-9 [doi]
• Frequency-Domain Transient Electromigration Analysis Using Circuit TheoryMohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar. 1-8 [doi]
• MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL DesignWenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie. 1-9 [doi]
• Automated Synthesis for In-Memory ComputingMuhammad Rashedul Haq Rashed, Sven Thijssen, Sumit Kumar Jha 0001, Rickard Ewetz. 1-9 [doi]
• Reliable Hyperdimensional Reasoning on Unreliable Emerging TechnologiesHamza Errahmouni Barkam, Sanggeon Yun, Hanning Chen, Paul Gensler, Albi Mema, Andrew Ding, George Michelogiannakis, Hussam Amrouch, Mohsen Imani. 1-9 [doi]
• Checkpoint Placement for Systematic Fault-Injection CampaignsChristian Dietrich 0001, Tim-Marek Thomas, Matthias Mnich. 1-9 [doi]
• Technology Mapping Using Multi-Output Library CellsAlessandro Tempia Calvino, Giovanni De Micheli. 1-9 [doi]
• ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based ImplementationSiyuan Liang, Meng Lian, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho. 1-9 [doi]
• DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP CircuitsRongliang Fu, Olivia Chen, Bei Yu 0001, Nobuyuki Yoshikawa, Tsung-Yi Ho. 1-8 [doi]
• Accuracy-Preserving Reduction of Sparsified Reduced Power Grids with A Multilevel Node Aggregation SchemeZhiqiang Liu, Wenjian Yu. 1-9 [doi]
• SAM: A Scalable Accelerator for Number Theoretic Transform Using Multi-Dimensional DecompositionCheng Wang, Mingyu Gao. 1-9 [doi]
• IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space ExplorationZiyang Yu, Chen Bai, Shoubo Hu, Ran Chen, Taohai He, Mingxuan Yuan, Bei Yu 0001, Martin D. F. Wong. 1-9 [doi]
• Invited Paper: Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-OffYufei Chen, Xiao Dong, Wei-Kai Shih, Cheng Zhuo. 1-6 [doi]
• PRIMO: A Full-Stack Processing-in-DRAM Emulation Framework for Machine Learning WorkloadsJaehoon Heo, Yongwon Shin, Sangjin Choi, Sungwoong Yune, Jung Hoon Kim, Hyojin Sung, Youngjin Kwon, Joo-Young Kim. 1-9 [doi]
• SSDe: FPGA-Based SSD Express Emulation FrameworkYizhen Lu, Luyang Yu, Deming Chen. 1-9 [doi]
• HF-Dedupe: Hierarchical Fingerprint Scheme for High Efficiency Data Deduplication on Flash-based Storage SystemsKai-Ting Weng, Yun-Shan Hsieh, Yen-Ting Chen, Yu-Pei Liang, Yuan-Hao Chang 0001, Po-Chun Huang, Wei Kuan Shih. 1-9 [doi]
• ACOR: On the Design of Energy-Efficient Autocorrelation for Emerging Edge ApplicationsCharalampos Eleftheriadis, Georgios Karakonstantis. 1-9 [doi]
• Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit OptimizationJintao Li, Haochang Zhi, Weiwei Shan, Yongfu Li, Yanhan Zeng, Yun Li. 1-9 [doi]
• Invited Paper: Algorithm/Hardware Co-Design for Few-Shot Learning at the EdgeAnn Franchesca Laguna, Mohammad Mehdi Sharifi, Dayane Reis, Liu Liu, Andrew Hennessee, Clayton O'Dell, Ian O'Connor, Michael T. Niemier, X. Sharon Hu. 1-9 [doi]
• TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC OperationsDengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun 0003. 1-9 [doi]
• AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAPZhuoping Yang, Jinming Zhuang, Jiaqi Yin, Cunxi Yu, Alex K. Jones, Peipei Zhou 0001. 1-9 [doi]
• OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM CircuitsYanfang Liu, Guohao Dai, Yuanqing Cheng, Wang Kang, Wei W. Xing. 1-9 [doi]
• BeKnight: Guarding Against Information Leakage in Speculatively Updated Branch PredictorsMd Hafizul Islam Chowdhuryy, Zhenkai Zhang, Fan Yao. 1-9 [doi]
• HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation TechniqueJai-Ming Lin, Yu-Chien Lin, Hsuan Kung, Wei-Yuan Lin. 1-8 [doi]
• Multi-Objective Architecture Search and Optimization for Heterogeneous Neuromorphic ArchitectureJuseong Park, Yongwon Shin, Hyojin Sung. 1-8 [doi]
• SurgeFuzz: Surge-Aware Directed Fuzzing for CPU DesignsYuichi Sugiyama, Reoma Matsuo, Ryota Shioya. 1-9 [doi]
• Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous PlatformsXun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang. 1-9 [doi]
• Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL DesignsYingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu. 1-4 [doi]
• FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector DataflowThilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh. 1-9 [doi]
• Invited Paper: Programming Dynamic Task Parallelism for Heterogeneous EDA AlgorithmsCheng-Hsiang Chiu, Dian-Lun Lin, Tsung-Wei Huang. 1-8 [doi]
• Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled CircuitsMingfei Yu, Giovanni De Micheli. 1-9 [doi]
• LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory ArchitectureLibo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang 0009, Yinhe Han 0001, Xiaoming Chen 0003. 1-9 [doi]
• NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural NetworkZhiyang Chen, Tsung-Yi Ho, Ulf Schlichtmann, Datao Chen, Mingyu Liu, Hailong Yao, Xia Yin. 1-9 [doi]
• Invited Paper: Machine Learning Based Blind Side-Channel Attacks on PQC-Based KEMs - A Case Study of Kyber KEMPrasanna Ravi, Dirmanto Jap, Shivam Bhasin, Anupam Chattopadhyay. 1-7 [doi]
• Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based SystemsBharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique 0001. 1-9 [doi]
• Distributionally Robust Circuit Design Optimization under Variation ShiftsYifan Pan, Zichang He, Nanlin Guo, Zheng Zhang 0005. 1-8 [doi]
• Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 ProcessZonghao Li, Anthony Chan Carusone. 1-9 [doi]
• Power-Aware Training for Energy-Efficient Printed Neuromorphic CircuitsHaibin Zhao, Priyanjana Pal, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. 1-9 [doi]
• Automatic Inductive Invariant Generation for Scalable Dataflow Circuit VerificationJiahui Xu, Lana Josipovic. 1-9 [doi]
• DeepGate2: Functionality-Aware Circuit Representation LearningZhengyuan Shi, Hongyang Pan, Sadaf Khan, Min Li 0019, Yi Liu, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Zhufei Chu, Qiang Xu 0001. 1-9 [doi]
• Routability-Driven Orientation-Aware Analytical Placement for System in PackageJai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen. 1-8 [doi]
• HAPIC: A Scalable, Lightweight and Reactive Cache for Persistent-Memory-Based IndexChih-Ting Lo, Yun-Chih Chen, Yuan-Hao Chang 0001, Tei-Wei Kuo. 1-7 [doi]
• Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory DevicesJuejian Wu, Tianyu Liao, Taixin Li, Yixin Xu, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, Xueqing Li. 1-9 [doi]
• A Point Transformer Accelerator with Fine-Grained Pipelines and Distribution-Aware Dynamic FPSYaoxiu Lian, Xinhao Yang, Ke Hong, Yu Wang 0002, Guohao Dai, Ningyi Xu. 1-9 [doi]
• Thermally-Aware Multi-Core Chiplet StackingGaurav Kothari, Kanad Ghose. 1-9 [doi]
• TaintFuzzer: SoC Security Verification using Taint Inference-enabled FuzzingMuhammad Monir Hossain, Nusrat Farzana Dipu, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor. 1-9 [doi]