A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology

Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang. A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. In IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022. pages 251-255, IEEE, 2022. [doi]

Abstract

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