0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS

Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. In Jacqueline Snyder, Rakesh Patel, Tom Andre, editors, IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings. pages 1-4, IEEE, 2010. [doi]

Abstract

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