0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS

Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. In Jacqueline Snyder, Rakesh Patel, Tom Andre, editors, IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings. pages 1-4, IEEE, 2010. [doi]

@inproceedings{OkumaIRZCWTS10,
  title = {0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS},
  author = {Yasuyuki Okuma and Koichi Ishida and Yoshikatsu Ryu and Xin Zhang and Po-Hung Chen and Kazunori Watanabe and Makoto Takamiya and Takayasu Sakurai},
  year = {2010},
  doi = {10.1109/CICC.2010.5617586},
  url = {http://dx.doi.org/10.1109/CICC.2010.5617586},
  researchr = {https://researchr.org/publication/OkumaIRZCWTS10},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings},
  editor = {Jacqueline Snyder and Rakesh Patel and Tom Andre},
  publisher = {IEEE},
  isbn = {978-1-4244-5758-8},
}