Table of Contents

• VTS 2004 Best Innovative Practices Session Award [doi]
• Program Committee [doi]
• Foreword [doi]
• Test Technology Technical Council [doi]
• Steering Committee [doi]
• Reviewers [doi]
• Organizing Committee [doi]
• VTS 2004 Best Paper Award [doi]
• VTS 2004 Best Panel Award [doi]
• Test Technology Educational Program: Overview of Tutorials [doi]
• Acknowledgments [doi]
• A Built-in Self-Test Method for Write-only Content Addressable MemoriesDilip K. Bhavsar. 9-14 [doi]
• Flash Memory Built-In Self-Diagnosis with Test Mode ControlJen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin. 15-20 [doi]
• Highly Configurable Programmable Built-In Self Test Architecture for High-Speed MemoriesIsmet Bayraktaroglu, Olivier Caty, Yickkei Wong. 21-26 [doi]
• Transition Tests for High Performance MicroprocessorsYi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee. 29-34 [doi]
• On Silicon-Based Speed Path IdentificationLeonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak. 35-41 [doi]
• At-Speed Transition Fault Testing With Low Speed Scan EnableNisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic. 42-47 [doi]
• Minimal March Tests for Unlinked Static Faults in Random Access MemoriesGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian. 53-59 [doi]
• Modeling and Testing Comparison Faults for Ternary Content Addressable MemoriesJin-Fu Li, Chou-Kun Lin. 60-65 [doi]
• SRAM Retention Testing: Zero Incremental Time Integration with March AlgorithmsBaosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian. 66-71 [doi]
• Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment CapabilitiesDarren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt. 75-84 [doi]
• Cantilever Type Probe Card for At-Speed Memory Test on WaferHitoshi Iwai, Atsushi Nakayama, Naoko Itoga, Kotaro Omata. 85-89 [doi]
• Low Cost Scheme for On-Line Clock Skew CompensationMartin Omaña, Daniele Rossi, Cecilia Metra. 90-95 [doi]
• Implementing a Scheme for External Deterministic Self-TestAbdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel. 101-106 [doi]
• On A Software-Based Self-Test Methodology and Its ApplicationCharles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Kai Yang, Wei-Ting Liu, Ji-Jan Chen. 107-113 [doi]
• Synthesis of X-Tolerant Convolutional CompactorsJanusz Rajski, Jerzy Tyszer. 114-119 [doi]
• An Efficient Random Jitter Measurement Technique Using Fast Comparator SamplingDongwoo Hong, Cameron Dryden, Gordon Saksena. 123-130 [doi]
• On-Chip Spectrum Analyzer for Analog Built-In Self TestAnup P. Jose, Keith A. Jenkins, Scott K. Reynolds. 131-136 [doi]
• Production Test Methods for Measuring Out-of-Band Interference of Ultra Wide Band (UWB) DevicesSoumendu Bhattacharya, Abhijit Chatterjee. 137-142 [doi]
• Towards an Understanding of No Trouble Found DevicesScott Davidson. 147-152 [doi]
• Reducing Pattern Delay Variations for Screening Frequency Dependent DefectsBenjamin N. Lee, Li-C. Wang, Magdy S. Abadir. 153-160 [doi]
• Effective TARO Pattern GenerationIntaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey. 161-166 [doi]
• A New Algorithm for Dynamic Faults Detection in RAMsMohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg. 177-182 [doi]
• Data Retention Fault in SRAM Memories: Analysis and Detection ProceduresLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan. 183-188 [doi]
• Test and Characterization of a Variable-Capacity Multilevel DRAMJohn C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott. 189-197 [doi]
• A BIST Scheme for FPGA Interconnect Delay FaultsChun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu. 201-206 [doi]
• Soft Error Mitigation for SRAM-Based FPGAsGhazanfar Asadi, Mehdi Baradaran Tahoori. 207-212 [doi]
• On-Chip Electro-Thermal Stimulus Generation for a MEMS-Based Magnetic Field SensorNorbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet. 213-218 [doi]
• Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case StudyMatthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press. 223-228 [doi]
• Pseudo-Functional Scan-based BIST for Delay FaultYung-Chieh Lin, Feng Lu, Kwang-Ting Cheng. 229-234 [doi]
• Static Compaction of Delay Tests Considering Power Supply NoiseJing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker. 235-240 [doi]
• Built-In Test of RF Components Using Mapped Feature Extraction SensorsSelim Sermet Akbay, Abhijit Chatterjee. 243-248 [doi]
• A CMOS RF RMS Detector for Built-in Testing of Wireless TransceiversAlberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio. 249-254 [doi]
• Low-Cost Alternate EVM Test for Wireless Receiver SystemsAchintya Halder, Abhijit Chatterjee. 255-260 [doi]
• On Low-Capture-Power Test Generation for Scan TestingXiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita. 265-270 [doi]
• Reduction of Instantaneous Power by Ripple Scan ClockingKirti Joshi, Eric MacDonald. 271-276 [doi]
• Jump Scan: A DFT Technique for Low Power TestingMin-Hao Chiu, Chien-Mo James Li. 277-282 [doi]
• Survey of Design and Process Failure Modes for High-Speed SerDes in Nanometer CMOSCameron Dryden. 285-291 [doi]
• Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOSQikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy. 292-297 [doi]
• Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error ToleranceAbdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh. 298-303 [doi]
• Synthesis of Low Power CED Circuits Based on Parity CodesShalini Ghosh, Sugato Basu, Nur A. Touba. 315-320 [doi]
• Defect Tolerance for Gracefully-Degradable Microfluidics-Based BiochipsFei Su, Krishnendu Chakrabarty. 321-326 [doi]
• Closed-Form Simulation and Robustness Models for SEU-Tolerant DesignKartik Mohanram. 327-333 [doi]
• Experimental Evaluation of Bridge Patterns for a High Performance MicroprocessorSreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee. 337-342 [doi]
• Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron TechnologiesIlia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker. 343-348 [doi]
• Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip ClockingChunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota. 349-354 [doi]
• Hierarchical Compactor Design for Diagnosis in Deterministic Logic BISTPeter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew. 359-365 [doi]
• Diagnosis of Arbitrary Defects Using Neighborhood Function ExtractionRao Desineni, R. D. (Shawn) Blanton. 366-373 [doi]
• Diagnosis of Failing Component in RF Receivers through Adaptive Full-Path MeasurementsErkan Acar, Sule Ozev. 374-379 [doi]
• A BIST Scheme for Testing Analog-to-Digital Converters with Digital Response AnalysesYun-Che Wen. 383-388 [doi]
• Testing the Interconnect Networks and I/O Resources of Field Programmable Analog ArraysGustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell. 389-394 [doi]
• Constructive Derivation of Analog Specification Test CriteriaHaralampos-G. D. Stratigopoulos, Yiorgos Makris. 395-400 [doi]
• Segmented Addressable Scan ArchitectureAhmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck. 405-411 [doi]
• An Economic Selecting Model for DFT StrategiesYu-Ting Lin, Tony Ambler. 412-417 [doi]
• Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level CircuitsLoganathan Lingappan, Niraj K. Jha. 418-423 [doi]
• Defect Screening Using Independent Component Analysis on I_DDQRitesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch. 427-432 [doi]
• Hardware Results Demonstrating Defect Detection Using Power Supply Signal MeasurementsDhruva Acharyya, Jim Plusquellic. 433-438 [doi]
• Pattern Generation and Estimation for Power Supply Noise AnalysisMehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed. 439-444 [doi]