Abstract is missing.
- Hybrid FPGA ArchitectureAlireza Kaviani, Stephen Dean Brown. 3-9 [doi]
- Plasma: An FPGA for Million Gate SystemsRick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider, Lyle Albertson. 10-16 [doi]
- Using BDDs to Design ULMs for FPGAsZeljko Zilic, Zvonko G. Vranesic. 24-30 [doi]
- Universal Logic Modules for Series-Parallel FunctionsShashidhar Thakur, D. F. Wong. 31-37 [doi]
- Combined Spectral Techniques for Boolean MatchingE. Schubert, Wolfgang Rosenstiel. 38-43 [doi]
- The Wave Pipeline Effect on LUT-Based FPGA ArchitecturesEduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses. 45-50 [doi]
- Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate ArraysVi Cuong Chan, David M. Lewis. 51-57 [doi]
- Technology Mapping of Sequential Circuits for LUT-Based FPGAs for PerformancePeichen Pan, C. L. Liu. 58-64 [doi]
- A Method for Generating Random Circuits and Its Application to Routability MeasurementJoel Darnauer, Wayne Wei-Ming Dai. 66-72 [doi]
- Entropy, Counting, and Programmable InterconnectAndré DeHon. 73-79 [doi]
- Universal Switch-Module Design for Symmetric-Array-Based FPGAsYao-Wen Chang, D. F. Wong, C. K. Wong. 80-86 [doi]
- Diagnosing Programmable Interconnect Systems for FPGAsFabrizio Lombardi, David Ashen, Xiao-Tao Chen, Wei-Kang Huang. 100-106 [doi]
- Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic BlocksCharles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici. 107-113 [doi]
- DPGA Utilization and ApplicationAndré DeHon. 115-121 [doi]
- Sequencing Run-Time Reconfigured Hardware with SoftwareMichael J. Wirthlin, Brad L. Hutchings. 122-128 [doi]
- Computing the Discrete Fourier Transform on FPGA Based Systolic ArraysChris Dick. 129-135 [doi]
- RASP: A General Logic Synthesis System for SRAM-Based FPGAsJason Cong, John Peck, Yuzheng Ding. 137-143 [doi]
- Emerald: An Architecture-Driven Tool Compiler for FPGAsDarren C. Cronquist, Larry McMurchie. 144-150 [doi]
- Structured Design Implementation: A Strategy for Implementing Regular Datapaths on FPGAsAndreas Koch. 151-157 [doi]