Horng-Fei Jyu - researchr alias

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Viewing Publication 1 - 5 from 5

1995

Prediction of interconnect delay in logic synthesisHorng-Fei Jyu, Sharad Malik. date 1995: 411-417 [doi]

1994

Statistical Delay Modeling in Logic Design and SynthesisHorng-Fei Jyu, Sharad Malik. dac 1994: 126-130 [doi]

1993

Statistical Timing Optimization of Combinatorial Logic CircuitsHorng-Fei Jyu, Sharad Malik. iccd 1993: 77-80

Statistical timing analysis of combinational logic circuitsHorng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer. tvlsi, 1(2):126-137, 1993. [doi]

1992

Statistical Timing Analysis of Combinational CircuitsSrinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik. iccd 1992: 38-43

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