Table of Contents

• A novel design framework for the design of reconfigurable systems based on NoCsVincenzo Rana, Donatella Sciuto. 1-2 [doi]
• A new physical routing approach for robust bundled signaling on NoC linksMohammad Reza Kakoee, Igor Loi, Luca Benini. 3-8 [doi]
• Bus via reduction based on floorplan revisingOu He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng. 9-14 [doi]
• Timing-driven variation-aware nonuniform clock mesh synthesisAmeer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman. 15-20 [doi]
• Scaling power/ground solvers on multi-core with memory bandwidth awarenessJin Shi, Yici Cai. 21-26 [doi]
• Bus-pin-aware bus-driven floorplanningBo-Shiun Wu, Tsung-Yi Ho. 27-32 [doi]
• 8Gb/s capacitive low power and high speed 4-PWAM transceiver designYoung Bok Kim, Yong-Bin Kim, Fabrizio Lombardi. 33-38 [doi]
• A low power, variable resolution two-step flash ADCMahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 39-44 [doi]
• A low-offset high-speed double-tail dual-rail dynamic latched comparatorHeungJun Jeon, Yong-Bin Kim. 45-48 [doi]
• Via configurable three-input lookup-tables for structured ASICsYu-Chen Chen, Hou-Yu Pang, Kuen-Wen Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su. 49-54 [doi]
• Variation tolerant 9T SRAM cell designSreeharsha Tavva, Dhireesha Kudithipudi. 55-60 [doi]
• Stochastic computational models for accurate reliability evaluation of logic circuitsHao Chen, Jie Han. 61-66 [doi]
• A multi-level approach to reduce the impact of NBTI on processor functional unitsTaniya Siddiqua, Sudhanva Gurumurthi. 67-72 [doi]
• Graph theoretic approach for scan cell reordering to minimize peak shift powerJaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara. 73-78 [doi]
• Gating internal nodes to reduce power during scan shiftDheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas. 79-84 [doi]
• Software adaptation in quality sensitive applications to deal with hardware variabilityAashish Pant, Puneet Gupta, Mihaela van der Schaar. 85-90 [doi]
• Write activity reduction on flash main memory via smart victim cacheLiang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Xuehai Zhou, Edwin Hsing-Mean Sha. 91-94 [doi]
• Aging effects of leakage optimizations for cachesAndrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino. 95-98 [doi]
• Thermal-aware floorplanning exploration for 3D multi-core architecturesDavid Cuesta, José Luis Ayala, Jose Hidalgo, Massimo Poncino, Andrea Acquaviva, Enrico Macii. 99-102 [doi]
• A mask double patterning technique using litho simulation by wavelet transformRance Rodrigues, Sandip Kundu. 103-106 [doi]
• An effective approach for large scale floorplanningAmeya R. Agnihotri, Satoshi Ono, Patrick H. Madden. 107-110 [doi]
• A novel resource sharing model and high-level synthesis for delay variability-tolerant datapathsKeisuke Inoue, Mineo Kaneko. 111-114 [doi]
• A revisit to voltage partitioning problemTao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto. 115-118 [doi]
• Resource-constrained timing-driven link insertion for critical delay reductionJin-Tai Yan, Zhi-Wei Chen. 119-122 [doi]
• Boolean satisfiability on a graphics processorKanupriya Gulati, Sunil P. Khatri. 123-126 [doi]
• Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metricJunxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard. 127-130 [doi]
• Improving the testability and reliability of sequential circuits with invariant logicNuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar. 131-134 [doi]
• Deterministic broadside test generation for transition path delay faultsBo Yao, Irith Pomeranz, Sudhakar M. Reddy. 135-138 [doi]
• A delay measurement method using a shrinking clock signalJae-Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham. 139-142 [doi]
• Energy-efficient redundant execution for chip multiprocessorsPramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson. 143-146 [doi]
• On-die sensors for measuring process and environmental variations in integrated circuitsKanak Agarwal. 147-150 [doi]
• Cost aware fault tolerant logic synthesis in presence of soft errorsXin He, Afshin Abdollahi. 151-154 [doi]
• Design of embedded MRAM macros for memory-in-logic applicationsSumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer. 155-158 [doi]
• Topology impact on the room temperature performance of THz-range ballistic deflection transistorsVikas Kaushal, Ignacio Iñiguez-de-la-Torre, Martin Margala. 159-162 [doi]
• Performance assessment of analog circuits with carbon nanotube FET (CNFET)Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi. 163-166 [doi]
• Read-out schemes for a CNTFET-based crossbar memorySheng Lin, Yong-Bin Kim, Fabrizio Lombardi. 167-170 [doi]
• Synthetic biology: from modules to systemsRon Weiss. 171-172 [doi]
• Dominant critical gate identification for power and yield optimization in logic circuitsMihir R. Choudhury, Masoud Rostami, Kartik Mohanram. 173-178 [doi]
• Logic synthesis for low power using clock gating and rewiringTak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu. 179-184 [doi]
• Dynamically resizable binary decision diagramsStergios Stergiou, Jawahar Jain. 185-190 [doi]
• Fast instruction cache modeling for approximate timed HW/SW co-simulationJuan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez. 191-196 [doi]
• Clock skew reduction by self-compensating manufacturing variability with on-chip sensorsShinya Abe, Kenichi Shinkai, Masanori Hashimoto, Takao Onoye. 197-202 [doi]
• Online convex optimization-based algorithm for thermal management of MPSoCsFrancesco Zanini, David Atienza, Giovanni De Micheli, Stephen P. Boyd. 203-208 [doi]
• Overscaling-friendly timing speculation architecturesJohn Sartori, Rakesh Kumar. 209-214 [doi]
• A model to exploit power-performance efficiency in superscalar processors via structure resizingOmer Khan, Sandip Kundu. 215-220 [doi]
• Thermal-aware compilation for system-on-chip processing architecturesMohamed M. Sabry, José L. Ayala, David Atienza. 221-226 [doi]
• A linear statistical analysis for full-chip leakage power with spatial correlationRuijing Shen, Sheldon X.-D. Tan, Jinjun Xiong. 227-232 [doi]
• Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistorsXuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, Kartik Mohanram. 233-238 [doi]
• Lightweight runtime control flow analysis for adaptive loop cachingMarisha Rawlins, Ann Gordon-Ross. 239-244 [doi]
• Low power nanoscale buffer management for network on chip routersSuman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra. 245-250 [doi]
• TURBONFS: turbo nand flash searchShruti Vyas, Aswin Sreedhar, Sandip Kundu. 251-256 [doi]
• Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded systemSoontae Kim, Jongmin Lee. 257-262 [doi]
• Graphene tunneling FET and its applications in low-power circuit designXuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram. 263-268 [doi]
• Scalable identification of threshold logic functionsAshok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas. 269-274 [doi]
• Manufacturing yield of QCA circuits by synthesized DNA self-assembled templatesXiaojun Ma, Masoud Hashempour, Lei Wang, Fabrizio Lombardi. 275-280 [doi]
• Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devicesPooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky. 281-286 [doi]
• Design considerations for variation tolerant multilevel CMOS/Nano memristor memoryHarika Manem, Garrett S. Rose, Xiaoli He, Wei Wang. 287-292 [doi]
• An integrated thermal estimation framework for industrial embedded platformsAndrea Acquaviva, Andrea Calimera, Alberto Macii, Massimo Poncino, Enrico Macii, Matteo Giaconia, Claudio Parrella. 293-298 [doi]
• Power-efficient, reliable microprocessor architectures: modeling and design methodsPradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban. 299-304 [doi]
• Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCsMohamed M. Sabry, Martino Ruggiero, Pablo Garcia Del Valle. 305-310 [doi]
• A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicoresAndrea Bartolini, Matteo Cacciari, Andrea Tilli, Luca Benini, Matthias Gries. 311-316 [doi]
• Challenges and methodologies for efficient power budgeting across the diePinkesh J. Shah, Yoni Aizik, Muhammad K. Mhameed, Gila Kamhi. 317-322 [doi]
• A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAMGarima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan. 323-328 [doi]
• Line width optimization for interdigitated power/ground networksRenatas Jakushokas, Eby G. Friedman. 329-334 [doi]
• Thermal-aware voltage droop compensation for multi-core architecturesJia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier. 335-340 [doi]
• Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performanceBasab Datta, Wayne Burleson. 341-346 [doi]
• Collaborative voltage scaling with online STA and variable-latency datapathTay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu. 347-352 [doi]
• AOP-based high-level power estimation in SystemCFeng Liu, Qingping Tan, Xiaoyu Song, Naeem Abbasi. 353-356 [doi]
• A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemesShanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu. 357-360 [doi]
• The challenges of implementing fine-grained power gatingAnja Niedermeier, Kjetil Svarstad, Frank Bouwens, Jos Hulzink, Jos Huisken. 361-364 [doi]
• Performance and energy efficient cache migrationapproach for thermal management in embedded systemsRaid Ayoub, Alex Orailoglu. 365-368 [doi]
• Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffersSumanth Amarchinta, Dhireesha Kudithipudi. 369-372 [doi]
• Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOSAnuj Pushkarna, Hamid Mahmoodi. 373-376 [doi]
• On-chip point-of-load voltage regulator for distributed power suppliesSelcuk Kose, Eby G. Friedman. 377-380 [doi]
• VLSI implementation of a non-linear feedback shift register for high-speed cryptography applicationsPey-Chang Kent Lin, Sunil P. Khatri. 381-384 [doi]
• Out-of-order issue logic using sorting networksSiddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski. 385-388 [doi]
• On-chip power supply noise and its implications on timingLars J. Svensson, Johnny Pihl, Daniel A. Andersson, Per Larsson-Edefors. 389-392 [doi]
• Characteristics of MS-CMOS logic in sub-32nm technologiesKagan Irez, Jiaping Hu, Charles A. Zukowski. 393-396 [doi]
• A self-adaptive scheduler for asymmetric multi-coresOmer Khan, Sandip Kundu. 397-400 [doi]
• Context-aware TLB preloading for interference reduction in embedded multi-tasked systemsIlya Chukhman, Peter Petrov. 401-404 [doi]
• Design of self correcting radiation hardened digital circuits using decoupled ground busSohan Purohit, Sai Rahul Chalamalasetti, Martin Margala. 405-408 [doi]
• A novel multi-objective instruction synthesis flow for application-specific instruction set processorsHai Lin, Yunsi Fei. 409-412 [doi]
• Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnectsAnkit More, Baris Taskin. 413-416 [doi]
• Ordered escape routing via routability-driven pin assignmentJin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen. 417-422 [doi]
• Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package designDe-Yu Liu, Wai-Kei Mak, Ting-Chi Wang. 423-428 [doi]
• Performance-constrained template-driven retargeting for analog and RF layoutsZheng Liu, Lihong Zhang. 429-434 [doi]
• Wirelength-driven force-directed 3D FPGA placementWentao Sui, Sheqin Dong, Jinian Bian. 435-440 [doi]
• A novel droplet routing algorithm for digital microfluidic biochipsPranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta. 441-446 [doi]
• Methodology to achieve higher tolerance to delay variations in synchronous circuitsEmre Salman, Eby G. Friedman. 447-452 [doi]
• Circuit-level NBTI macro-models for collaborative reliability monitoringBasab Datta, Wayne P. Burleson. 453-458 [doi]
• Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystemsJun Wu, Yong-Bin Kim, Minsu Choi. 459-464 [doi]
• Enhancing debugging of multiple missing control errors in reversible logicJean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler. 465-470 [doi]
• Algorithm and hardware complexity reduction techniques for k-best sphere decodersNariman Moezzi Madani, Thorlindur Thorolfsson, William Rhett Davis. 471-476 [doi]