Gating internal nodes to reduce power during scan shift

Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas. Gating internal nodes to reduce power during scan shift. In R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand, editors, Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010. pages 79-84, ACM, 2010. [doi]

Abstract

Abstract is missing.