Abstract is missing.
- Constructing exact octagonal steiner minimal treesChris Coulston. 1-6 [doi]
- Bounding the efforts on congestion optimization for physical synthesisDavide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas. 7-10 [doi]
- A comprehensive high-level synthesis system for control-flow intensive behaviorsWeidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha. 11-14 [doi]
- Iterative decoding in analog CMOSSaied Hemati, Amir H. Banihashemi. 15-20 [doi]
- Design issues in low-voltage high-speed current-mode logic buffersPayam Heydari. 21-26 [doi]
- Optimum wire sizing of RLC interconnect with repeatersMagdy A. El-Moursy, Eby G. Friedman. 27-32 [doi]
- Reduced dynamic swing domino logicRoy Mader, Ivan S. Kourtev. 33-36 [doi]
- A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technologyChao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald. 37-40 [doi]
- Interconnected rings and oscillators as gigahertz clock distribution netsManuel Salim Maza, Mónico Linares Aranda. 41-44 [doi]
- Information storage capacity of crossbar switching networksPaul-Peter Sotiriadis. 45-49 [doi]
- Exploiting multiple functionality for nano-scale reconfigurable systemsPaul Beckett. 50-55 [doi]
- CMOS flash analog-to-digital converter for high speed and low voltage applicationsJincheol Yoo, Kyusun Choi, Jahan Ghaznavi. 56-59 [doi]
- Modeling QCA for area minimization in logic synthesisNadine Gergel, Shana Craft, John Lach. 60-63 [doi]
- Power-aware pipelined multiplier design based on 2-dimensional pipeline gatingJia Di, Jiann S. Yuan. 64-67 [doi]
- Low power VLSI sequential circuit architecture using critical race controlMenahem Lowy, Neal Butler, Rosanne Tinkler. 68-71 [doi]
- A hybrid adiabatic content addressable memory for ultra low-power applicationsAiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier. 72-75 [doi]
- TEM-cell and surface scan to identify the electromagnetic emission of integrated circuitsTimm Ostermann, Bernd Deutschmann. 76-79 [doi]
- MuTaTe: an efficient design for testability technique for multiplexor based circuitsRolf Drechsler, Junhao Shi, Görschwin Fey. 80-83 [doi]
- Cooling of integrated circuits using droplet-based microfluidicsVamsee K. Pamula, Krishnendu Chakrabarty. 84-87 [doi]
- Language emptiness checking using MDGsFang Wang, Sofiène Tahar. 88-91 [doi]
- A system-level methodology for fast multi-objective design space explorationGianluca Palermo, Cristina Silvano, S. Valsecchi, Vittorio Zaccaria. 92-95 [doi]
- A practical CAD technique for reducing power/ground noise in DSM circuitsArindam Mukherjee, Krishna Reddy Dusety, Rajsaktish Sankaranarayan. 96-99 [doi]
- RF CMOS circuit optimizing procedure and synthesis toolChandrasekar Rajagopal, Karthik Sridhar, Adrian Nunez. 100-103 [doi]
- Wirelength reduction by using diagonal wireCharles Chiang, Qing Su, Ching-Shoei Chiang. 104-107 [doi]
- A fast simulation approach for inductive effects of VLSI interconnectsXiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-dong Yang, Sangwoo Kim, Stephan Mueller, Hendrik Mau, Lawrence T. Pileggi. 108-111 [doi]
- Buffer sizing for minimum energy-delay product by using an approximating polynomialChang Woo Kang, Soroush Abbaspour, Massoud Pedram. 112-115 [doi]
- FORCE: a fast and easy-to-implement variable-ordering heuristicFadi A. Aloul, Igor L. Markov, Karem A. Sakallah. 116-119 [doi]
- Routing methodology for minimizing 1nterconnect energy dissipationAtsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura. 120-123 [doi]
- Circuit design of a wide tuning range CMOS VCO with automatic amplitude controlJiwei Chen, Bingxue Shi. 124-127 [doi]
- A decoupling technique for CMOS strong-coupled structuresLi Yang, J. S. Yuan. 128-131 [doi]
- A custom FPGA for the simulation of gene regulatory networksIlias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou. 132-135 [doi]
- A novel architecture for power maskable arithmetic unitsLuca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro. 136-140 [doi]
- 3D direct vertical interconnect microprocessors test vehicleJohn Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald, Russell P. Kraft. 141-146 [doi]
- Zero overhead watermarking technique for FPGA designsAdarsh K. Jain, Lin Yuan, Pushkin R. Pari, Gang Qu. 147-152 [doi]
- Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithmGeoff Knagge, David Garrett, Sivarama Venkatesan, Chris Nicol. 153-156 [doi]
- System level design of real time face recognition architecture based on composite PCARajkiran Gottumukkal, Vijayan K. Asari. 157-160 [doi]
- Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor arrayJianhua Gan, Shouli Yan, Jacob A. Abraham. 161-164 [doi]
- Shielding effect of on-chip interconnect inductanceMagdy A. El-Moursy, Eby G. Friedman. 165-170 [doi]
- A pipelined clock-delayed domino carry-lookahead adderBhushan A. Shinkre, James E. Stine. 171-175 [doi]
- A globally asynchronous locally dynamic system for ASICs and SoCsAtanu Chattopadhyay, Zeljko Zilic. 176-181 [doi]
- 40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applicationsMichael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock. 182-185 [doi]
- Design topology aware physical metrics for placement analysisShyam Ramji, Nagu R. Dhanwada. 186-191 [doi]
- A novel ultra-fast heuristic for VLSI CAD steiner treesBharat Krishna, C. Y. Roger Chen, Naresh Sehgal. 192-197 [doi]
- Combining wire swapping and spacing for low-power deep-submicron busesEnrico Macii, Massimo Poncino, Sabino Salerno. 198-202 [doi]
- Clustering based acyclic multi-way partitioningEric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak. 203-206 [doi]
- Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routingHua Tang, Hui Zhang, Alex Doboli. 207-210 [doi]
- Congestion reduction in traditional and new routing architecturesAmeya R. Agnihotri, Patrick H. Madden. 211-214 [doi]
- Simultaneous peak and average power minimization during datapath scheduling for DSP processorsSaraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi. 215-220 [doi]
- Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designsNoureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria. 221-224 [doi]
- Branch prediction techniques for low-power VLIW processorsGianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon. 225-228 [doi]
- 54x54-bit radix-4 multiplier based on modified booth algorithmKi-seon Cho, Jong-on Park, Jin-seok Hong, Goang-seog Choi. 233-236 [doi]
- Power-time flexible architecture for GF(2:::k:::) elliptic curve cryptosystem computationAdnan Abdul-Aziz Gutub, Mohammad K. Ibrahim. 237-240 [doi]
- A novel 32-bit scalable multiplier architectureYeshwant Kolla, Yong-Bin Kim, John Carter. 241-244 [doi]
- High throughput overlapped message passing for low density parity check codesYanni Chen, Keshab K. Parhi. 245-248 [doi]
- Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizersEdward Merlo, Kwang-Hyun Baek, Myung-Jun Choe. 249-252 [doi]
- Using dynamic domino circuits in self-timed systemsJung-Lin Yang, Erik Brunvand. 253-256 [doi]
- Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designsFrank Grassert, Dirk Timmermann. 257-260 [doi]
- Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logicDavid Harris, Genevieve Breed, Matt Erler, David Diaz. 261-264 [doi]
- Variable gain amplifier with offset cancellationAhmed Emira, Edgar Sánchez-Sinencio. 265-268 [doi]
- Repeater and current-sensing hybrid circuits for on-chip interconnectsAtul Maheshwari, Wayne Burleson. 269-272 [doi]
- A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuitRam Suryanarayan, Anubhav Gupta, Travis N. Blalock. 273-276 [doi]
- A dual band CMOS VCO with a balanced duty cycle bufferYun Cheol Han, Kwang il Kim, Jun Kim, Kwang Sub Yoon. 277-280 [doi]
- New approach to CMOS current reference with very low temperature coefficientJiwei Chen, Bingxue Shi. 281-284 [doi]
- Noise tolerant low voltage XOR-XNOR for fast arithmeticMohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi. 285-288 [doi]
- On automatic generation of RTL validation test benches using circuit testing techniquesIndradeep Ghosh, Srivaths Ravi. 289-294 [doi]
- A highly regular multi-phase reseeding technique for scan-based BISTEmmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos. 295-298 [doi]
- Coefficient-based parametric faults detection in analog circuitsZhen Guo. 299-302 [doi]
- Mixing ATPG and property checking for testing HW/SW interfacesAlessandro Fin, Franco Fummi, Graziano Pravadelli. 303-306 [doi]