Table of Contents

• DFM: swimming upstreamDan Page, Jamil Kawa, Charles Chiang. 1 [doi]
• Design approaches for hybrid CMOS/molecular memory based on experimental device dataGarrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour. 2-7 [doi]
• Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementationsRui Zhang, Niraj K. Jha. 8-13 [doi]
• Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologiesXiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal. 14-18 [doi]
• Thermal analysis of a 3D die-stacked high-performance microprocessorKiran Puttaswamy, Gabriel H. Loh. 19-24 [doi]
• HW/SW partitioning techniques for multi-mode multi-task embedded applicationsYoung-Jun Kim, Taewhan Kim. 25-30 [doi]
• ISS-centric modular HW/SW co-simulationFranco Fummi, Giovanni Perbellini, Mirko Loghi, Massimo Poncino. 31-36 [doi]
• An ILP based approach to address code generation for digital signal processorsOzcan Ozturk, Mahmut T. Kandemir, Suleyman Tosun. 37-42 [doi]
• HW/SW co-verification of embedded systems using bounded model checkingDaniel Große, Ulrich Kühne, Rolf Drechsler. 43-48 [doi]
• PWAM signalling scheme for high speed serial link transceiver designRui Tang, Yong-Bin Kim. 49-52 [doi]
• High speed differential pulse-width control loop based on frequency-to-voltage convertersHung Tien Bui, Yvon Savaria. 53-56 [doi]
• Synthesis of a wideband low noise amplifierAbhishek Jajoo, Michael Sperling, Tamal Mukherjee. 57-62 [doi]
• A 0.13::::::µm:::::: CMOS 10 Gb/s current-mode class AB serial link transmitter with low supply voltage sensitivityMinghai Li, Fei Yuan. 63-66 [doi]
• Dominator-based partitioning for delay optimizationDavid Bañeres, Jordi Cortadella, Michael Kishinevsky. 67-72 [doi]
• How does partitioning matter for 3D floorplanning?Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani. 73-78 [doi]
• Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAsChang Woo Kang, Massoud Pedram. 79-84 [doi]
• Shuttle mask floorplanning with modified alpha-restricted gridRoyce L. S. Ching, Evangeline F. Y. Young. 85-90 [doi]
• Delay and Power Estimation Models of Low-Swing Interconnects for Design PlanningXiangyuan Liu, Shuming Chen. 91-94 [doi]
• A simulation methodology for reliability analysis in multi-core SoCsAyse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf Leblebici, Giovanni De Micheli. 95-99 [doi]
• Power density minimization for highly-associative caches in embedded processorsJa Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail. 100-104 [doi]
• An evaluation of the impact of gate oxide tunneling on dual-::::V::t::::::-based leakage reduction techniquesLara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud. 105-110 [doi]
• Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reductionJiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra. 111-114 [doi]
• General transistor-level methodology on VLSI low-power designZuying Luo. 115-118 [doi]
• Delay and peak power minimization for on-chip buses using temporal redundancyK. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam. 119-122 [doi]
• Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technologyZhiyuan Li, Fengchang Lai, Mingyan Yu. 123-126 [doi]
• A new power-area efficient 4-PAM full-clock CMOS pre-emphasis transmitter for 10Gb/s serial linksFei Yuan. 127-130 [doi]
• A low-power and high-linear double-balanced switching mixerJun-Da Chen, Zhi-Ming Lin. 131-134 [doi]
• Nonlinearity Analysis in ISD CMOS LNA s Using Volterra SeriesYarallah Koolivand, Omid Shoaei, A. Fotowat-Ahmadi, Ali Zahabi, Parviz Jabedar-Maralani. 135-139 [doi]
• On-chip 3.3V-to-1.8V voltage down converter for low-power VLSI chipsQianneng Zhou, Fengchang Lai, Mingyan Yu. 140-143 [doi]
• A SiGe BiCMOS linear regulator with wideband, high power supply rejectionHung D. Nguyen, Benjamin J. Blalock, Suheng Chen. 144-148 [doi]
• Optimizing noise-immune nanoscale circuits using principles of Markov random fieldsKundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky. 149-152 [doi]
• Dynamic instruction schedulers in a 3-dimensional integration technologyKiran Puttaswamy, Gabriel H. Loh. 153-158 [doi]
• Yield enhancement of asynchronous logic circuits through 3-dimensional integration technologySong Peng, Rajit Manohar. 159-164 [doi]
• Effects of process and environmental variations on timing characteristics of clocked registersWilliam R. Roberts, Dimitrios Velenis. 165-168 [doi]
• On finding the minimum test set of a BDD-based circuitGopal Paul, Ajit Pal, Bhargab B. Bhattacharya. 169-172 [doi]
• Maximum effective distance of on-chip decoupling capacitors in power distribution gridsMikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu. 173-179 [doi]
• Implementation of MOSFET based capacitors for digital applicationsBo Shen, Sunil P. Khatri, Takis Zourntos. 180-186 [doi]
• Efficient modeling of integrated narrow-band low noise amplifiers for design space explorationTamer Ragheb, Arthur Nieuwoudt, Yehia Massoud. 187-191 [doi]
• Sensitivity evaluation of global resonant H-tree clock distribution networksJonathan Rosenfeld, Eby G. Friedman. 192-197 [doi]
• 2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technologyRashed Zafar Bhatti, Monty Denneau, Jeff Draper. 198-203 [doi]
• Implementation analysis of NoC: a MPSoC trace-driven approachSergio Tota, Mario R. Casu, Luca Macchiarulo. 204-209 [doi]
• From single core to multi-core to many core: are we ready for a new exponential?Jeff Parkhurst. 210 [doi]
• Techniques for improved placement-coupled logic replicationHosung (Leo) Kim, John Lillis, Milos Hrkic. 211-216 [doi]
• A design flow to optimize circuit delay by using standard cells and PLAsRajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri. 217-222 [doi]
• Statistical gate delay calculation with crosstalk alignment considerationAndrew B. Kahng, Bao Liu, Xu Xu. 223-228 [doi]
• Towards formal probabilistic power-performance design space explorationJoonsoo Kim, Michael Orshansky. 229-234 [doi]
• An indirect current sensing technique for IDDQ and IDDT testsChuen-Song Chen, Jien-Chung Lo, Tian Xia. 235-240 [doi]
• SACI: statistical static timing analysis of coupled interconnectsHanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer. 241-246 [doi]
• Performance verification of high-performance ASICs using at-speed structural testVikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor, Frank Woytowich. 247-252 [doi]
• Crosstalk analysis in nanometer technologiesShahin Nazarian, Ali Iranli, Massoud Pedram. 253-258 [doi]
• Using Lin-Kernighan algorithm for look-up table compression to improve code densityTalal Bonny, Jörg Henkel. 259-265 [doi]
• FPGA implementation of a parallel EBCOT tier-1 encoder that preserves coding efficiencyHima B. Damecharla, Kamal K. Varma, Joan Carletta, Amy E. Bell. 266-271 [doi]
• Partial parallel factorization in soft-decision Reed-Solomon decodingXinmiao Zhang. 272-277 [doi]
• Monotonic static CMOS tradeoffs in sub-100nm technologiesAli Bastani, Charles A. Zukowski. 278-283 [doi]
• A power optimized design methodology for low-distortion sigma-delta-pipeline ADCsVahid Majidzadeh, Omid Shoaei. 284-289 [doi]
• Perception-guided power minimization for color sequential displaysWei-Chung Cheng, Chain-Fu Chao. 290-295 [doi]
• Evaluation of on-chip networks using deflection routingZhonghai Lu, Mingchen Zhong, Axel Jantsch. 296-301 [doi]
• A digit serial algorithm for the integer power operationLun Li, Mitchell A. Thornton, David W. Matula. 302-307 [doi]
• Resource and delay efficient matrix multiplication using newer FPGA devicesScott J. Campbell, Sunil P. Khatri. 308-311 [doi]
• Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codesYongmei Dai, Zhiyuan Yan, Ning Chen. 312-315 [doi]
• Energy-delay minimization in nanoscale domino logicBo Fu, Qiaoyan Yu, Paul Ampadu. 316-319 [doi]
• High throughput architecture for H.264/AVC forward transforms blockLuciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva. 320-323 [doi]
• Hardware/software partitioning of operating systems: a behavioral synthesis approachSathish Chandra, Francesco Regazzoni, Marcello Lajolo. 324-329 [doi]
• A practical approach for monitoring analog circuitsMohamed H. Zaki, Sofiène Tahar, Guy Bois. 330-335 [doi]
• A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effectsXu Zhang, Xiaohong Jiang, Susumu Horiguchi. 336-340 [doi]
• A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy ModelsJinwen Xi, Peixin Zhong. 341-344 [doi]
• A formal approach for high level synthesis of linear analog systemsSoumya Pandit, Chittaranjan A. Mandal, Amit Patra. 345-348 [doi]
• Transformation synthesis for data intensive applications to FPGAsRenqiu Huang, Ranga Vemuri. 349-352 [doi]
• An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCsMohamed El-Nozahi, Yehia Massoud. 353-356 [doi]
• A heuristic algorithm to minimize ESOPs for multiple-output incompletely specified functionsMarios Kalathas, Dimitrios Voudouris, George K. Papakonstantinou. 357-361 [doi]
• Test generation using SAT-based bounded model checking for validation of pipelined processorsHeon-Mo Koo, Prabhat Mishra. 362-365 [doi]
• An efficient algorithm for partitioning parameterized polygons into rectanglesI-Lun Tseng, Adam Postula. 366-371 [doi]
• Application of fast SOCP based statistical sizing in the microprocessor design flowMurari Mani, Mahesh Sharma, Michael Orshansky. 372-375 [doi]
• Block alignment in 3D floorplan using layered TCGJill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching. 376-380 [doi]
• Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modelingPaul Sotiriadis, Abdullah Celik, Zhaonian Zhang. 381-385 [doi]
• Selective code/data migration for reducing communication energy in embedded MpSoC architecturesOzcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy. 386-391 [doi]
• Dynamic voltage scaling for multitasking real-time systems with uncertain execution timeChangjiu Xian, Yung-Hsiang Lu. 392-397 [doi]
• Low-power cache organization through selective tag translation for embedded processors with virtual memory supportXiangrong Zhou, Peter Petrov. 398-403 [doi]
• STV-Cache: a leakage energy-efficient architecture for data cachesKimish Patel, Luca Benini, Enrico Macii, Massimo Poncino. 404-409 [doi]
• A design methodology for temperature variation insensitive low power circuitsRanjith Kumar, Volkan Kursun. 410-415 [doi]
• Circuit architecture for low-power race-free programmable logic arraysGiby Samson, Lawrence T. Clark. 416-421 [doi]
• An energy-efficient temporal encoding circuit technique for on-chip high performance busesQingli Zhang, Jinxiang Wang, Yizheng Ye. 422-427 [doi]
• Leakage current starved domino logicZhiyu Liu, Volkan Kursun. 428-433 [doi]