Yizheng Ye - researchr alias

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Viewing Publication 1 - 32 from 32

2012

Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test CostBin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu, Bei Cao. jolpe, 8(1):73-81, 2012. [doi]

2011

Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice OverlappingBin Zhou, Liyi Xiao, Yizheng Ye, Xin-chun Wu. et, 27(1):43-56, 2011. [doi]

2010

Exact BER Analysis of Differential Chaos Shift Keying Communication System in Fading ChannelsZhibo Zhou, Jinxiang Wang, Yizheng Ye. wpc, 53(2):299-310, 2010. [doi]

A test set embedding approach based on twisted-ring counter with few seedsBin Zhou, Yizheng Ye, Zhao-lin Li, Jianwei Zhang, Xin-chun Wu, Rui Ke. integration, 43(1):81-100, 2010. [doi]

2009

2008

A Fully Integrated CMOS Active Bandpass Filter for Multiband RF Front-EndsZhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye. tcas, 55-II(8):718-722, 2008. [doi]

Delay and Energy Efficient Design of On-Chip Encoded Bus with RepeatersQingli Zhang, Jinxiang Wang, Yizheng Ye. vlsid 2008: 377-382 [doi]

A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable MemoriesJianwei Zhang, Yizheng Ye, Bin-Da Liu. tvlsi, 16(6):677-682, 2008. [doi]

2007

Simultaneous reduction in test data volume and test time for TRC-reseedingBin Zhou, Yizheng Ye, Yong-sheng Wang. glvlsi 2007: 49-54 [doi]

2006

A CMOS bandpass filter with wide-tuning range for wireless applicationsZhiqiang Gao, Mingyan Yu, Yizheng Ye, Jianguo Ma. iscas 2006: [doi]

Post linearization of CMOS LNA using double cascade FETsGuochi Huang, Tae Sung Kim, Byung-Sung Kim, Mingyan Yu, Yizheng Ye. iscas 2006: [doi]

Dependency driven partitioning objects generation for hardware/software partitioningShengtian Sang, Xiaoming Li, Yizheng Ye. iscas 2006: [doi]

Low-Power Crosstalk Avoidance Encoding for On-Chip Data BusesQingli Zhang, Jinxiang Wang, Yizheng Ye. apccas 2006: 1611-1614 [doi]

An energy-efficient temporal encoding circuit technique for on-chip high performance busesQingli Zhang, Jinxiang Wang, Yizheng Ye. glvlsi 2006: 422-427 [doi]

A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMsJianwei Zhang, Yizheng Ye, Bin-Da Liu. islped 2006: 135-138 [doi]

A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable MemoriesJianwei Zhang, Yizheng Ye, Bin-Da Liu. apccas 2006: 1293-1296 [doi]

A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto ProcessorTong Zhou, Mingyan Yu, Yizheng Ye. vlsid 2006: 216-221 [doi]

Design of A Low Power High Entropy Chaos-Based Truly Random Number GeneratorTong Zhou, Zhibo Zhou, Mingyan Yu, Yizheng Ye. apccas 2006: 1955-1958 [doi]

2005

2003

A Test Architecture for System-on-a-ChipYong-sheng Wang, Liyi Xiao, Mingyan Yu, Jinxiang Wang, Yizheng Ye. ats 2003: 506 [doi]

2002

A New Synchronization Algorithm for VHDL-AMS SimulationLiyi Xiao, Yizheng Ye, Bin Li. jcst, 17(1):28-37, 2002. [doi]

Design and implementation of concatenated decoderYuxin You, Jinxiang Wang, Mingyan Yu, Yizheng Ye. dcv 2002: 135-142 [doi]

Design and Realization of a Low Power Register File Using Energy ModelXuemei Zhao, Yizheng Ye. patmos 2002: 268-277 [doi]

2001

CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit SimulationBin Li, Liyi Xiao, Yizheng Ye, Guoyong Huang. anss 2001: 78 [doi]

A mixed-signal simulator for VHDL-AMSLiyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang. aspdac 2001: 287-292 [doi]

2000

Implementation of Java Card Virtual MachineLiu Songyan, Zhigang Mao, Yizheng Ye. jcst, 15(6):591-596, 2000. [doi]

1999

A New Algorithm for Retiming-Based Partial ScanZulan Huang, Yizheng Ye, Zhigang Mao. ats 1999: 327 [doi]

1998

Test Pattern Generation for Column Compression MultiplierPingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng. ats 1998: 500-503 [doi]

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1998

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