Table of Contents

• 3.48mW 2.4GHz range Frequency Synthesizer Architecture with Two-Point Channel Control for Fast Settling PerformanceSangho Shin, Kwyro Lee, Sung-Mo Kang. 1-6 [doi]
• A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link ApplicationsRam Kelkar, Dave Flye, Anjali Malladi, Joseph Natonio, Chri Scoville, Ken Short, Pradeep Thiagarajan. 7-10 [doi]
• 3.125Gbps Reference-less Clock and Data Recovery using 4X OversamplingSung-Sop Lee, Hyung-Wook Jang, Jin-Ku Kang. 11-14 [doi]
• Digital clock frequency doublerSanjay Kumar Wadhwa, Qadeer Ahmad Khan, Kulbhushan Misri, Deeya Muhury. 15-18 [doi]
• Power minimization of rotary clock designZhengtao Yu 0002, Xun Liu. 19-24 [doi]
• Thermal-aware mapping and placement for 3-D NoC designsCharles Addo-Quaye. 25-28 [doi]
• An IR drop-driven placer for standard cells in a SOC designJun Cheng Chi, Tsung Hui Huang, Mely Chen Chi. 29-32 [doi]
• Combined simulator statistics and block code sampling to study performance enhancement of microarchitectureHuibin Shi, Chris Bailey, Glenn Farrall, Neil Hastie, Sam Jenkins. 33-36 [doi]
• A CMOS Voltage Reference with Temperature Sensor using Self-PTAT Current CompensationChih-Peng Liu, Han-Pang Huang. 37-42 [doi]
• Hybrid Voltage and Current References Based on Double ZTC PointsChih-Peng Liu, Han-Pang Huang. 43-46 [doi]
• Automatic gain control circuit for power line communication applicationChung-Yuan Chen, Tai-Ping Sun. 47-50 [doi]
• CMOS SoC for irrigation controlJosé Camargo da Costa, Adson Ferreira da Rocha, Leonardo R. A. X. de Menezes, Ricardo Pezzuol Jacobi, Alexandre R. S. Romariz, R. R. P. Soares, Gilmar S. Beserra, J. D. Costa, Genival Mariano de Araujo, W. A. Araujo, J. C. Sd. S. Marra, W. A. Amaral, P. R. O. Vogel, A. L. da Silva, A. Jd. O. Martins, L. R. Povoa. 51-54 [doi]
• A Flow Graph Technique for DFT Controller ModificationMohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi. 55-60 [doi]
• Testing system-on-a-chip using artificial immune systemCleonilson Protásio de Souza, Raimundo Carlos Silvério Freire, Francisco Marcos de Assis. 61-64 [doi]
• Improving Error Resilience for Compressed Test Sets by Don't Care AssignmentHamidreza Hashempour, Fabrizio Lombardi. 65-68 [doi]
• Hybrid test data compression technique for SOC scan testingSangwook Cho, Jaehoon Song, Hyunbean Yi, Sungju Park. 69-72 [doi]
• A low jitter delay-locked loop with a realignment duty cycle correctorLarry Li, Hou-Ming Chen, Robert Chen-Hao Chang. 73-76 [doi]
• 1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technologyHai Qi Liu, Wang Ling Goh, Liter Siek. 77-78 [doi]
• A CMOS RF tuning wide-band bandpass filter for wireless applicationsZhiqiang Gao, Jianguo Ma, Mingyan Yu, Yizheng Ye. 79-80 [doi]
• Reliability-aware floorplanning for 3D circuitsJacob R. Minz, Eric Wong, Sung Kyu Lim. 81-82 [doi]
• Synchronous latency-insensitive design for multiple clock domainAnders Edman, Christer Svensson, Behzad Mesgarzadeh. 83-86 [doi]
• Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architectureJun-Hee Mun, Muling Peng, Sangjin Hong, Alex Doboli, K. Wendy Tang. 87-88 [doi]
• Constraint-based Code mapping for heterogeneous Chip multiprocessorsSuleyman Tosun, Nazanin Mansouri, Mahmut T. Kandemir, Özcan Özturk. 89-90 [doi]
• Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video CodingTiago Dias, Nuno Roma, Leonel Sousa. 91-92 [doi]
• Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applicationsCheng Zhan, Sami Khawam, Tughrul Arslan, Iain Lindsay. 93-94 [doi]
• Precharged SRAM cell for ultra low-power on-chip cacheRamy E. Aly, Magdy A. Bayoumi. 95-98 [doi]
• GPSDVS: An improved task-based dynamic voltage scaling scheme for general-purpose systemsSookyoung Kim, Thomas L. Martin. 99-100 [doi]
• A novel five-transistor (5T) sram cell for high performance cacheMichael Wieckowski, Martin Margala. 101-102 [doi]
• Improved memory strategy for logmap turbo decodersImran Ahmed, Tughrul Arslan, Sajid Baloch. 103-104 [doi]
• Accurate Simulation Environment for Signal Isolation in Mixed-Signal DesignSuman K. Banerjee, Radu M. Secareanu, Eric Nabity, Alain Duvallet, Olin L. Hartin. 105-108 [doi]
• Support for multiprocessor synchronization and resource sharing in system-on-programmable chips with softcoresPaolo Gai, Giuseppe Lipari, Marco Di Natale, Matteo Duranti, Alberto Ferrari. 109-110 [doi]
• Mapping of partial reconfigurable data flows to Xilinx FPGAsAkshay Athalye, Sangjin Hong. 111-112 [doi]
• A Low Power Heterogenous Reconfigurable Architecture For Embedded Generic Finite State MachinesZhenyu Liu, Tughrul Arslan, Sami Khawam, Ahmet T. Erdogan. 113-114 [doi]
• FPGA-based vector processor for algebraic equation solversHongyan Yang, Sotirios G. Ziavras. 115-116 [doi]
• Novel VLSI architecture of motion estimation for H.264 standardXiang Li, Rahul Chopra, Kenneth W. Hsu. 117-118 [doi]
• Integrated assignment of registers and functional units for heterogeneous vliw-architecturesThomas Zeitlhofer, Bernhard Wess. 119-124 [doi]
• Simultaneous memory and bus partitioning for SoC architecturesSuresh Srinivasan, Federico Angiolini, Martino Ruggiero, Luca Benini, Narayanan Vijaykrishnan. 125-128 [doi]
• Resource allocation methodology for the segmented bus platformTiberiu Seceleanu, Ville Leppänen, Jyri Suomi, Olli Nevalainen. 129-132 [doi]
• System Level Design Methodology for System On Chips using Multi-Threaded GraphsSyed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla. 133-136 [doi]
• Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routingAjay Joshi, Jeffrey A. Davis. 137-142 [doi]
• A New Breed of Power-Aware Hybrid ShiftersRaghavan Ramadoss. 143-146 [doi]
• Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strengthHarmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka. 147-150 [doi]
• Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide TunnelingZhiyu Liu, Volkan Kursun. 151-154 [doi]
• Workload Clustering for Increasing Energy Savings on Embedded MPSoCsSri Hari Krishna Narayanan, Özcan Özturk, Mahmut T. Kandemir, Mustafa Karaköy. 155-160 [doi]
• Design and implementation of interface circuitry for cmos-based saw gas sensorsFaisal Mohd-Yasin, K. F. Tye, Mamun Bin Ibne Reaz. 161-164 [doi]
• DG-SRAM: a low leakage memory circuitPraveen Elakkumanan, Charan Thondapu, Ramalingam Sridhar. 167-170 [doi]
• Novel 7T sram cell for low power cache designRamy E. Aly, Md. Ibrahim Faisal, Magdy A. Bayoumi. 171-174 [doi]
• On-Chip Memory Management for Embedded MpSoC Architectures Based on Data CompressionÖzcan Özturk, Mahmut T. Kandemir, Mary Jane Irwin, Suleyman Tosun. 175-178 [doi]
• CMOS passive RFID transponder with read-only memory for low cost fabricationWoochul Jeon, John Melngailis, Robert W. Newcomb. 181-184 [doi]
• A band-switching wide-band CMOS LC QVCO for multi-standard applicationsJi-Hoon Kim, Hyung-Joun Yoo. 185-188 [doi]
• A 2 GHz and 5GHz dual-band direct conversion RF frontend for multi-standard applicationsYong-Seok Hwang, Sang-Sun Yoo, Hyung-Joun Yoo. 189-192 [doi]
• Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCsPaul Muller, Yusuf Leblebici. 193-196 [doi]
• Dynamic fraction control bus: new SOC on-chip communication architecture designNan Wang, Magdy A. Bayoumi. 199-202 [doi]
• Resistive Loss and Trans-Impedance Characterization of Nonlinear Transmission Lines on CMOS SOI SubstrateJinsook Kim, Weiping Ni, Edwin C. Kan. 203-206 [doi]
• Designing for signal integrity in wave-pipelined SOC global interconnectsVinita V. Deodhar, Jeffrey A. Davis. 207-210 [doi]
• An improved implementation method of AHB BusMatrixSoo Yun Hwang, Kyoung-Sun Jhang. 211-214 [doi]
• Effective IP reuse for high quality SOC designSoujanna Sarkar, Subash Chandar G, Sanjay Shinde. 217-224 [doi]
• Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate DesignsThi Nguyen, Kaijian Shi. 225-228 [doi]
• Including Power Supply Variations into Static Timing Analysis: Methodology and FlowMariagrazia Graziano, Cristiano Forzan, Davide Pandini. 229-232 [doi]
• Operating system support for dynamically reconfigurable SoC architecturesAlberto Donato, Fabrizio Ferrandi, Marco D. Santambrogio, Donatella Sciuto. 233-238 [doi]
• Online-adaptive Reconfigurable Hardware Architecture and Runtime EnvironmentAlexander Thomas, Jürgen Becker. 239-242 [doi]
• A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoCVijay K. Jain, Samit Bhanja, Glenn H. Chapman, Lavanya Doddannagari. 243-246 [doi]
• A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication SystemsJ. H. Han, Ahmet T. Erdogan, Tughrul Arslan. 247-250 [doi]
• A Clock Isolation Method For Complex SoC DesignsKaijian Shi, Hichem Belhadj. 251-256 [doi]
• A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS TechnologyChing-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu. 257-260 [doi]
• Bus Buffer Evaluation of Different Arbitration AlgorithmsXufan Wu, Jun Yang 0006, Longxing Shi. 261-264 [doi]
• Novel secret-key IPR protection in FPGA environmentBassel Soudan, Wael Adi, Abdulrahman Hanoun. 267-270 [doi]
• FPGA implementation of the "pyramids" block cipherAbdullah AlKalbany, Hussein Ahmad Al Hassan, Magdy Saeb. 271-275 [doi]
• A hierarchically-controlled SIMD machine for 2D DCT on FPGAsXizhen Xu, Sotirios G. Ziavras. 276-279 [doi]
• Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switchStephen O'Kane, Sakir Sezer, Ciaran Toal. 283-286 [doi]
• Hardware Design of Sphere Decoding for MIMO SystemsZhaohui Liu, Kevin Dickson, John V. McCanny. 287-290 [doi]
• Design and implementation of phase correlation based motion estimatorAndrea Molino, Fabrizio Vacca, Guido Masera. 291-294 [doi]
• Differential Pass Transistor Pulsed LatchMoo-young Kim, Inhwa Jung, Young-Ho Kwak, Sunghoon Ahn, Chulwoo Kim. 295-300 [doi]
• A High-Performance Router Design for VDSM NoCsAshok Narasimhan, Karthik Srinivasan, Ramalingam Sridhar. 301-304 [doi]
• A novel multiplier for high-speed applicationsAmir Khatibzadeh, Kaamran Raahemifar, Majid Ahmadi. 305-308 [doi]
• On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated CircuitsMikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. 309-312 [doi]
• I Models and Tools for the Dynamic Reconfiguration of FPGAsAdam Donlin, Jürgen Becker, Michael Hübner. 313-316 [doi]
• Serial RapidlO: Benefiting System InterconnectsTravis Scheckel. 317-318 [doi]
• Digital signal processors for communications, video infrastructure, and audioNat Seshan, Todd Hiers, Gustavo Martinez, Anthony Seely, Zoran Nikolic. 319-321 [doi]
• Standards-compliant IP-based ASIC and SoC designAmir Hekmatpour, Kenneth Goodnow, Hemen Shah. 322-323 [doi]
• High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOSHimanshu Kaul. 324 [doi]