Abstract is missing.
- A vector-pipeline DSP for low-rate videophonesKazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera. 1-2 [doi]
- A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing schemeHiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada. 3-4 [doi]
- Multi-hit time-to-digital converter VLSI for high-energy physics experimentsYasuo Arai. 5-6 [doi]
- A high-speed FIR digital filter with CSD coefficients implemented on FPGAMitsuru Yamada, Akinori Nishihara. 7-8 [doi]
- Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplificationYong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo. 9-10 [doi]
- A dynamically reconfigurable hardware-based cipher chipYukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa. 11-12 [doi]
- Test circuits for substrate noise evaluation in CMOS digital ICsMakoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata. 13-14 [doi]
- Realtime wavelet video coder based on reduced memory accessingRoberto Y. Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa. 15-16 [doi]
- A prototype chip of multicontext FPGA with DRAM for virtual hardwareDaisuke Kawakami, Yuichiro Shibata, Hideharu Amano. 17-18 [doi]
- A single-inductor dual-output integrated DC/DC boost converter for variable voltage schedulingDongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok. 19-20 [doi]
- A smart position sensor for 3-D measurementTomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada. 21-22 [doi]
- Parameterized MAC unit implementationMing-Chih Chen, Ing-Jer Huang, Chung-Ho Chen. 23-24 [doi]
- A parallel vector quantization processor featuring an efficient search algorithm for real-time motion picture compressionToshiyuki Nozawa, Makoto Imai, Masanori Fujibayashi, Tadahiro Ohmi. 25-26 [doi]
- An 8-b nRERL microprocessor for ultra-low-energy applicationsSeokkee Kim, Jun-Ho Kwon, Soo-Ik Chae. 27-28 [doi]
- Design and implementation of JPEG encoder IP coreChung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yung-Chi Chang. 29-30 [doi]
- A real-time 64-monosyllable recognition LSI with learning mechanismKazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe. 31-32 [doi]
- Reusable embedded in-circuit emulatorIng-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao. 33-34 [doi]
- Flexible processor based on full-adder/ d-flip-flop merged moduleSatoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi. 35-36 [doi]
- Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communicationTakanori Okuma, Koji Hashimoto, Kazuaki Murakami. 37-38 [doi]
- Correlation method of circuit-performance and technology fluctuations for improved design reliabilityD. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Michiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama. 39-44 [doi]
- Realization of semiconductor device synthesis with the parallel genetic algorithmZhao Li, Xiao-Feng Xie, Wenjun Zhang, Zhilian Yang. 45-49 [doi]
- Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talkMartin R. Frerichs. 50-56 [doi]
- Compiling SpecC for simulationJianwen Zhu, Daniel Gajski. 57-62 [doi]
- Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architecturesPatrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya. 63-68 [doi]
- A higher level system communication model for object-oriented specification and design of embedded systemsKjetil Svarstad, Nezih Ben-Fredj, Gabriela Nicolescu, Ahmed Amine Jerraya. 69-77 [doi]
- A dataflow specification for system level synthesis of 3D graphics applicationsChanik Park, Sungchan Kim, Soonhoi Ha. 78-84 [doi]
- The multiple variable order problem for binary decision diagrams: theory and practical applicationChristoph Scholl, Bernd Becker, Andreas Brogle. 85-90 [doi]
- Application of linearly transformed BDDs in sequential verificationWolfgang Günther, Andreas Hett, Bernd Becker. 91-96 [doi]
- A new partitioning scheme for improvement of image computationChristoph Meinel, Christian Stangier. 97-102 [doi]
- An efficient design-for-verification technique for HDLsChien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou. 103-108 [doi]
- Reducing bus delay in submicron technology using codingPaul-Peter Sotiriadis, Anantha Chandrakasan. 109-114 [doi]
- Optimal spacing and capacitance padding for general clock structuresYu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen. 115-119 [doi]
- Provably good global buffering by multi-terminal multicommodity flow approximationFeodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. 120-125 [doi]
- A construction of minimal delay Steiner tree using two-pole delay modelLiYi Lin, Yi-Yu Liu, TingTing Hwang. 126-132 [doi]
- New graph bipartizations for double-exposure, bright field alternating phase-shift mask layoutAndrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky. 133-138 [doi]
- Hierarchical dummy fill for process uniformityYu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky. 139-144 [doi]
- Modeling and forecasting of manufacturing variations (embedded tutorial)Sani R. Nassif. 145-150 [doi]
- A C-based synthesis system, Bach, and its application (invited talk)Takashi Kambe, Akihisa Yamada, Koichi Nishida, Kazuhisa Okada, Mitsuhisa Ohnishi, Andrew Kay, Paul Boca, Vince Zammit, Toshio Nomura. 151-155 [doi]
- Area/delay estimation for digital signal processor coresYuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 156-161 [doi]
- An RTL design-space exploration method for high-level applicationsPeng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu. 162-168 [doi]
- Equivalence checking of integer multipliersJiunn-Chern Chen, Yirng-An Chen. 169-174 [doi]
- Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkersG. Subash Chandar, S. Vaideeswaran. 175-180 [doi]
- An efficient solution to the storage correspondence problem for large sequential circuitsWanlin Cao, D. M. H. Walker, Rajarshi Mukherjee. 181-186 [doi]
- A 3-step approach for performance-driven whole-chip routingYih-Chih Chou, Youn-Long Lin. 187-191 [doi]
- Efficient minimum spanning tree construction without Delaunay triangulationHai Zhou, Narendra V. Shenoy, William Nicholls. 192-197 [doi]
- Memory-efficient interconnect optimizationMinghorng Lai, D. F. Wong. 198-202 [doi]
- Balanced truncation with spectral shaping for RLC interconnectsPayam Heydari, Massoud Pedram. 203-208 [doi]
- An optimum fitting algorithm for generation of reduced-order modelsMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney. 209-213 [doi]
- A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitanceZhaozhi Yang, Zeyi Wang, Shuzhou Fang. 214-218 [doi]
- On the minimization of SOPs for bi-decomposition functionsTsutomu Sasao, Jon T. Butler. 219-224 [doi]
- Finding an optimal functional decomposition for LUT-based FPGA synthesisJian Qiao, Makoto Ikeda, Kunihiro Asada. 225-230 [doi]
- Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocksKenneth Yan. 231-234 [doi]
- A new techology mapping for CPLD under the time constraintJae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin. 235-238 [doi]
- Power optimization and management in embedded systemsMassoud Pedram. 239-244 [doi]
- Low power techniques for address encoding and memory allocationWei-Chung Cheng, Massoud Pedram. 245-250 [doi]
- Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systemsVishnu Swaminathan, Krishnendu Chakrabarty. 251 [doi]
- The tangram framework (embedded tutorial): asynchronous circuits for low powerJoep L. W. Kessels, Ad M. G. Peeters. 255-260 [doi]
- Imprecise data computation for high performance asynchronous processorsJeong-Gun Lee, Euiseok Kim, Dong-Ik Lee. 261-266 [doi]
- Beyond the red brick wall (panel): challenges and solutions in 50nm physical designHidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori. 267-268 [doi]
- A pipelined ADC macro design for multiple applicationsKuniyuki Tani, Norihiro Nikai, Atsushi Wada, Tetsuro Sawai. 269-274 [doi]
- A dynamically phase adjusting PLL with a variable delayTakeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera. 275-280 [doi]
- Device-level placement for analog layout: an opportunity for non-slicing topological representationsFlorin Balasa. 281-286 [doi]
- A mixed-signal simulator for VHDL-AMSLiyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang. 287-292 [doi]
- Low power design challenges for the decade (invited talk)Shekhar Borkar. 293-296 [doi]
- An on-chip 96.5 current efficiency CMOS linear regulatorKazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka. 297-301 [doi]
- Reducing cache engery through dual voltage supplyVasily G. Moshnyaga. 302-305 [doi]
- Trace-driven system-level power evaluation of system-on-a-chip peripheral coresTony Givargis, Frank Vahid, Jörg Henkel. 306-312 [doi]
- Towards the logic defect diagnosis for partial-scan designsShi-Yu Huang. 313-318 [doi]
- Cellular automata as a built in self test structureBiplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri. 319-324 [doi]
- Processor-programmable memory BIST for bus-connected embedded memoriesChing-Hong Tsai, Cheng-Wen Wu. 325-330 [doi]
- A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testabilitySatoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara. 331-334 [doi]
- Timed circuits: a new paradigm for high-speed designChris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng. 335-340 [doi]
- Conformance and mirroring for timed asychronous circuitsBin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff. 341-346 [doi]
- Formal verification of pulse-mode asynchronous circuitsXiaohua Kong, Radu Negulescu. 347-352 [doi]
- A statistical static timing analysis considering correlations between delaysShuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui. 353-358 [doi]
- Post-layout transistor sizing for power reduction in cell-based designMasanori Hashimoto, Hidetoshi Onodera. 359-365 [doi]
- An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnectsWenjian Yu, Zeyi Wang. 366-372 [doi]
- Improved crosstalk modeling for noise constrained interconnect optimizationJason Cong, David Zhigang Pan, Prasanna V. Srinivas. 373-378 [doi]
- KSim: a stable and efficient RKC simulator for capturing on-chip inductance effectHao Ji, Anirudh Devgan, Wayne Wei-Ming Dai. 379-384 [doi]
- An efficient analytical model of coupled on-chip RLC interconnectsLiang Yin, Lei He. 385-390 [doi]
- RSA cryptosystem design based on the Chinese remainder theoremChung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu. 391-395 [doi]
- Speech recognition chip for monosyllablesKazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe. 396-399 [doi]
- Low power implementation of a turbo-decoder on programmable architecturesFrank Gilbert, Alexander Worm, Norbert Wehn. 400-403 [doi]
- Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modernHyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee. 404-408 [doi]
- New directions in compiler technology for embedded systems (embedded tutorial)Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi. 409-414 [doi]
- Optimized address assignment for DSPs with SIMD memory accessesMarkus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel. 415-420 [doi]
- A formal approach to component based development of synchronous programsPartha S. Roop, Arcot Sowmya, S. Ramesh. 421-424 [doi]
- Synthesis of four-phase asynchronous control circuits from pipeline dependency graphsHiroto Kagotani, Takuji Okamoto, Takashi Nanya. 425-430 [doi]
- High-level design for asynchronous logicRoss Smith, Michiel M. Ligthart. 431-436 [doi]
- Eliminating isochronic-fork constraints in quasi-delay-insensitive circuitsNattha Sretasereekul, Takashi Nanya. 437-442 [doi]
- Design technology productivity in the DSM era (invited talk)Andrew B. Kahng. 443-448 [doi]
- LEneS: task scheduling for low-energy systems using variable supply voltage processorsFlavius Gruian, Krzysztof Kuchcinski. 449-455 [doi]
- A system level memory power optimization technique using multiple supply and threshold voltagesTohru Ishihara, Kunihiro Asada. 456-461 [doi]
- Low-power high-level synthesis using latchesWoo-Seung Yang, In-Cheol Park, Chong-Min Kyung. 462-466 [doi]
- Functional extension of structural logic optimization techniquesJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías. 467-472 [doi]
- Improved alternative wiring scheme applying dominator relationshipChin-Ngai Sze, Yu-Liang Wu. 473-478 [doi]
- Design rewiring based on diagnosis techniquesAndreas G. Veneris, Magdy S. Abadir, Ivor Ting. 479-484 [doi]
- Design for testability strategies using full/partial scan designs and test point insertions to reduce test application timesToshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta. 485-491 [doi]
- A computer aided engineering system for memory BISTChauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee. 492-495 [doi]
- Synthesis of single-output space compactors with application to scan-based IP coresBhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty. 496-502 [doi]
- Slicing floorplan with clustering constraintsWing Seung Yuen, Fung Yu Young. 503-508 [doi]
- VLSI floorplanning with boundary constraints based on corner block listYuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu. 509-514 [doi]
- Module placement with boundary constraints using the sequence-pair representationJianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang. 515-520 [doi]
- FAST-SP: a fast algorithm for block placement based on sequence pairXiaoping Tang, D. F. Wong. 521-526 [doi]
- Toward better wireload models in the presence of obstaclesChung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt. 527-532 [doi]
- A fast and accurate delay estimation method for buffered interconnectsYouxin Gao, D. F. Wong. 533-538 [doi]
- On-chip interconnections: impact of adjacent lines on timingDenis Deschacht, Grégory Servel. 539-544 [doi]
- Short circuit power estimation of static CMOS circuitsSeung-Ho Jung, Jong-Humn Baek, Seok-Yoon Kim. 545-550 [doi]
- A novel network node architecture for high performance and function flexibilityTakahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki. 551-557 [doi]
- Virtual Java/FPGA interface for networked reconfigurationYajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man. 558-563 [doi]
- Coarse grain reconfigurable architecture (embedded tutorial)Reiner W. Hartenstein. 564-570 [doi]
- Efficient global fanout optimization algorithmsRajeev Murgai. 571-576 [doi]
- Timing driven gate duplication in technology independent phaseAnkur Srivastava, Chunhong Chen, Majid Sarrafzadeh. 577-582 [doi]
- On speeding up extended finite state machines using catalyst circuitryShi-Yu Huang. 583-588 [doi]
- Integrated power supply planning and floorplanningI-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong. 589-594 [doi]
- Post-layout timing-driven cell placement using an accurate net length model with movable Steiner pointsAmir H. Ajami, Massoud Pedram. 595-600 [doi]
- VLSI block placement using less flexibility first principlesSheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu. 601-604 [doi]
- A new congestion-driven placement algorithm based on cell inflationWenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao. 605-608 [doi]
- Cell selection from technology libraries for minimizing powerYumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen. 609-614 [doi]
- Low power optimization technique for BDD mapped circuitsPer Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler. 615-621 [doi]
- Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-addersYoungtae Kim, Taewhan Kim. 622-628 [doi]
- RPack: routability-driven packing for cluster-based FPGAsElaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh. 629-634 [doi]
- Power minization in LUT-based FPGA technology mappingZhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang. 635-640 [doi]
- Combinatorial routing analysis and design of universal switch blocksHongbing Fan, Jiping Liu, Yu-Liang Wu. 641-644 [doi]
- Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLABMalay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee. 645-648 [doi]
- Effectiveness of the ASIP design system PEAS-III in design of pipelined processorsAkira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai. 649-654 [doi]
- High-level specification and efficient implementation of pipelined circuitsMaria-Cristina V. Marinescu, Martin C. Rinard. 655-661 [doi]
- High-level synthesis under multi-cycle interconnect delayJinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi. 662 [doi]