Denis Deschacht - researchr alias

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Viewing Publication 1 - 16 from 16

2010

Crosstalk pulsewidth calculationJean-Etienne Lorival, Denis Deschacht. mj, 41(8):474-479, 2010. [doi]

2006

DSM interconnects: importance of inductance effects and corresponding range of lengthDenis Deschacht. tvlsi, 14(7):777-779, 2006. [doi]

2005

Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing OrientationDenis Deschacht, Alain Lopez. vlsid 2005: 640-643 [doi]

2004

Comparison between Different Data Buses ConfigurationsAlain Lopez, Denis Deschacht. isvlsi 2004: 69-76 [doi]

2002

Impact of Low-K on CrosstalkGrégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret. isqed 2002: 298-303 [doi]

2001

On-chip interconnections: impact of adjacent lines on timingDenis Deschacht, Grégory Servel. aspdac 2001: 539-544 [doi]

2000

Theoretical limits for signal reflections due to inductance for on-chip interconnectionsDenis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis. slip 2000: 55-60 [doi]

On-chip crosstalk evaluation between adjacent interconnectionsGrégory Servel, Denis Deschacht. icecsys 2000: 827-834 [doi]

1999

Inductance effect for interconnection timing analysis in submicronic circuitsGrégory Servel, L. B. Kenmei, Fabrice Huret, Erick Paleczny, Patrick Kennis, Denis Deschacht. icecsys 1999: 1407-1410 [doi]

1995

A new and accurate interconnection delay time evaluation in a general tree-type networkDenis Deschacht, Christophe Dabrin. aspdac 1995: [doi]

1993

Post-layout timing simulation of CMOS circuitsDenis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne. tcad, 12(8):1170-1177, 1993. [doi]

1991

Formal sizing rules of CMOS circuitsDaniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert. eurodac 1991: 96-100 [doi]

Synchronous-mode evaluation of delays in CMOS structuresDenis Deschacht, Michel Robert, Daniel Auvergne. jssc, 26(5):789-795, May 1991. [doi]

TVA: A timing verifier with analytic temporal modellingD. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne. jsa, 32(1-5):637-644, 1991. [doi]

1990

Input waveform slope effects in CMOS delaysDaniel Auvergne, Nadine Azémard, Denis Deschacht, Michel Robert. jssc, 25(6):1588-1590, December 1990. [doi]

Path runner: an accurate and fast timing analyserDenis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne. eurodac 1990: 529-533 [doi]

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