Abstract is missing.
- Design challenges for mobile communication devicesCristoph Kutter. 1 [doi]
- Analysis of super cut-off transistors for ultralow power digital logic circuitsArijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy. 2-7 [doi]
- Variation-driven device sizing for minimum energy sub-threshold circuitsJoyce Kwong, Anantha P. Chandrakasan. 8-13 [doi]
- Robust level converter design for sub-threshold logicIk Joon Chang, Jae-Joon Kim, Kaushik Roy. 14-19 [doi]
- Integrated solar energy harvesting and storageNathaniel J. Guilar, Albert Chen, Travis Kleeburg, Rajeevan Amirtharajah. 20-24 [doi]
- Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)Samuel Rodríguez, Bruce Jacob. 25-30 [doi]
- Stall cycle redistribution in a transparent fetch pipelineEric L. Hill, Mikko H. Lipasti. 31-36 [doi]
- Selective writeback: exploiting transient values for energy-efficiency and performanceDeniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose. 37-42 [doi]
- Energy-efficient dynamic instruction scheduling logic through instruction groupingHiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. 43-48 [doi]
- Independent front-end and back-end dynamic voltage scaling for a GALS microarchitectureGrigorios Magklis, Pedro Chaparro, José González, Antonio González. 49-54 [doi]
- Synergistic temperature and energy management in GALS processor architecturesYongKang Zhu, David H. Albonesi. 55-60 [doi]
- A two-port SRAM for real-time video processor saving 53 of bitline power with majority logic and data-bit reorderingHidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto. 61-66 [doi]
- A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boostingJonggab Kil, Jie Gu, Chris H. Kim. 67-72 [doi]
- A dual-V::DD:: boosted pulsed bus technique for low power and low leakage operationHarmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka. 73-78 [doi]
- Time-borrowing multi-cycle on-chip interconnects for delay variation toleranceKeith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De. 79-84 [doi]
- A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessorsPong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, R. Robertazzi, David F. Heidel. 85-88 [doi]
- Temporal vision-guided energy minimization for portable displaysWei-Chung Cheng, Chih-Fu Hsu, Chain-Fu Chao. 89-94 [doi]
- Dynamic current modeling at the instruction levelJose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley. 95-100 [doi]
- Reducing idle mode power in software defined radio terminalsHyunseok Lee, Trevor N. Mudge, Chaitali Chakrabarti. 101-106 [doi]
- Power reduction in an H.264 encoder through algorithmic and logic transformationsMaria G. Koziri, Georgios I. Stamoulis, Ioannis Katsavounidis. 107-112 [doi]
- Energy-efficient motion estimation using error-toleranceGirish Varatkar, Naresh R. Shanbhag. 113-118 [doi]
- Variability-aware device optimization under I::ON:: and leakage current constraintsJavid Jaffari, Mohab Anis. 119-122 [doi]
- A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V::::::T:::::: sense amplifiersRiichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi. 123-126 [doi]
- Utilizing reverse short channel effect for optimal subthreshold circuit designTae-Hyoung Kim, Hanyong Eom, John Keane, Chris H. Kim. 127-130 [doi]
- Logic circuits operating in subthreshold voltagesJabulani Nyathi, Brent Bero. 131-134 [doi]
- A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMsJianwei Zhang, Yizheng Ye, Bin-Da Liu. 135-138 [doi]
- Thread-associative memory for multicore and multithreaded computingShuo Wang, Lei Wang. 139-142 [doi]
- Hierarchical value cache encoding for off-chip data busChung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King. 143-146 [doi]
- Reducing cache traffic and energy with macro data loadLei Jin, Sangyeun Cho. 147-150 [doi]
- Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designsAxel Reimer, Arne Schulz, Wolfgang Nebel. 151-154 [doi]
- Thermal via allocation for 3D ICs considering temporally and spatially variant thermal powerHao Yu, Yiyu Shi, Lei He, Tanay Karnik. 156-161 [doi]
- Dynamic thermal clock skew compensation using tunable delay buffersAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 162-167 [doi]
- An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reductionYan Lin, Yu Hu, Lei He, Vijay Raghunat. 168-173 [doi]
- A novel approach for variation aware power minimization during gate sizingVenkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III. 174-179 [doi]
- Adaptive duty cycling for energy harvesting systemsJason Hsu, Sadaf Zahedi, Aman Kansal, Mani B. Srivastava, Vijay Raghunathan. 180-185 [doi]
- Power reduction of multiple disks using dynamic cache resizing and speed controlLe Cai, Yung-Hsiang Lu. 186-190 [doi]
- Lifetime aware resource management for sensor network using distributed genetic algorithmQinru Qiu, Qing Wu, Daniel J. Burns, Douglas Holzhauer. 191-196 [doi]
- Everlast: long-life, supercapacitor-operated wireless sensor nodeFarhan Simjee, Pai H. Chou. 197-202 [doi]
- Model to hardware matching: for nano-meter scale technologiesSani R. Nassif. 203-206 [doi]
- Low power light-weight embedded systemsMajid Sarrafzadeh, Foad Dabiri, Roozbeh Jafari, Tammara Massey, Ani Nahapetian. 207-212 [doi]
- Low power design from technology challenge to great productsBarry Dennington. 213 [doi]
- A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuitsBaozhen Yu, Michael L. Bushnell. 214-219 [doi]
- Analysis and modeling of subthreshold leakage of RT-components under PTV and state variationDomenik Helms, Günter Ehmen, Wolfgang Nebel. 220-225 [doi]
- Power optimization in a repeater-inserted interconnect via geometric programmingW. T. Cheung, N. Wong. 226-231 [doi]
- Input-specific dynamic power optimization for VLSI circuitsFei Hu, Vishwani D. Agrawal. 232-237 [doi]
- Two-phase fine-grain sleep transistor insertion technique in leakage critical circuitsYu Wang, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang. 238-243 [doi]
- Register file caching for energy efficiencyHui Zeng, Kanad Ghose. 244-249 [doi]
- L-CBF: a low-power, fast counting bloom filter architectureElham Safi, Andreas Moshovos, Andreas G. Veneris. 250-255 [doi]
- A low power SRAM architecture based on segmented virtual groundingMohammad Sharifkhani, Manoj Sachdev. 256-261 [doi]
- Process variation aware cache leakage managementKe Meng, Russ Joseph. 262-267 [doi]
- Substituting associative load queue with simple hash tables in out-of-order microprocessorsAlok Garg, Fernando Castro, Michael C. Huang, Daniel Chaver, Luis Piñuel, Manuel Prieto. 268-273 [doi]
- A novel power optimization technique for ultra-low power RFICsAmin Shameli, Payam Heydari. 274-279 [doi]
- A CMOS analog frontend for a passive UHF RFID tagAlessio Facen, Andrea Boni. 280-285 [doi]
- High-speed low-power frequency divider with intrinsic phase rotatorStephan Henzler, Siegmar Koeppe. 286-291 [doi]
- An optimal analytical solution for processor speed control with thermal constraintsRavishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang. 292-297 [doi]
- Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysisVidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar. 298-303 [doi]
- Power efficiency for variation-tolerant multicore processorsJames Donald, Margaret Martonosi. 304-309 [doi]
- Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architectureYoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek. 310-315 [doi]
- Dynamic thermal management for MPEG-2 decodingWonbok Lee, Kimish Patel, Massoud Pedram. 316-321 [doi]
- A low-power active substrate-noise decoupling circuit with feedforward compensation for mixed-signal SoCsSong Guo, Hoi Lee. 322-325 [doi]
- Power-efficient pulse width modulation DC/DC converters with zero voltage switching controlChangbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik. 326-329 [doi]
- Behavioral modeling of Opamp gain and dynamic effectsfor power optimization of Delta-Sigma modulators and pipelined ADCsAnas A. Hamoui, T. Alhajj, Mohammad Taherzadeh-Sani. 330-333 [doi]
- Low-power fanout optimization using MTCMOS and multi-Vt techniquesBehnam Amelifard, Farzan Fallah, Massoud Pedram. 334-337 [doi]
- A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuitsScott Hanson, Dennis Sylvester, David Blaauw. 338-341 [doi]
- Considering process variations during system-level power analysisSaumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey. 342-345 [doi]
- Synchronization-driven dynamic speed scaling for MPSoCsMirko Loghi, Massimo Poncino, Luca Benini. 346-349 [doi]
- Power phase variation in a commercial server workloadW. L. Bircher, L. K. John. 350-353 [doi]
- Reducing power through compiler-directed barrier synchronization eliminationMahmut T. Kandemir, Seung Woo Son. 354-357 [doi]
- Minimizing energy consumption of banked memories using data recomputationHakduran Koc, Ozcan Ozturk, Mahmut T. Kandemir, Sri Hari Krishna Narayanan, Ehat Ercanli. 358-362 [doi]
- Energy optimality and variability in subthreshold designScott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang. 363-365 [doi]
- Sub-threshold design: the challenges of minimizing circuit energyBenton H. Calhoun, Alice Wang, Naveen Verma, Anantha Chandrakasan. 366-368 [doi]
- Design and power management of energy harvesting embedded systemsVijay Raghunathan, Pai H. Chou. 369-374 [doi]
- Flexibility and low power: a contradiction in terms?Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson. 375 [doi]
- Efficient scan-based BIST scheme for low power testing of VLSI chipsMalav Shah. 376-381 [doi]
- Modeling and analysis of leakage induced damping effect in low voltage LSIsJie Gu, John Keane, Chris H. Kim. 382-387 [doi]
- Dithering skip modulator with a novel load sensor for ultra-wide-load high-efficiency DC-DC convertersHong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, Sy-Yen Kuo. 388-393 [doi]
- Adaptive on-chip power supply with robust one-cycle control techniqueDongsheng Ma, Janet Meiling Wang, Pablo Vazquas. 394-399 [doi]
- Robust multiple-phase switched-capacitor DC-DC converter with digital interleaving regulation schemeDongsheng Ma. 400-405 [doi]
- A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applicationsJie Jin, Chi-Ying Tsui. 406-411 [doi]
- SmartSaver: turning flash drive into a disk energy saver for mobile computersFeng Chen, Song Jiang, Xiaodong Zhang. 412-417 [doi]
- An energy-efficient virtual memory system with flash memory as the secondary storageHung-Wei Tseng, Han-Lin Li, Chia-Lin Yang. 418-423 [doi]
- Maximizing the lifetime of embedded systems powered by fuel cell-battery hybridsJianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula. 424-429 [doi]