Table of Contents

• Title Page [doi]
• Foreword [doi]
• Embedded Test Technology - Brief History, Current Status, and Future DirectionsJanusz Rajski. [doi]
• Copyright [doi]
• DFT Aware Layout - Layout Aware DFTSanjiv Taneja. [doi]
• Program Committee [doi]
• Advisory Board and Organizing Committee [doi]
• Faults and Tests in Quantum CircuitsJohn P. Hayes. [doi]
• T2: Statistical Methods for VLSI Test and Burn-in OptimizationAdit D. Singh. [doi]
• ATS Steering Committee [doi]
• TTTC Introduction [doi]
• Improving Logic Test Quality of MicroprocessorsSreejit Chakravarty. [doi]
• Best Paper Awards (2002 and 2003) [doi]
• Reviewers [doi]
• T1: Design for ManufacturabilityYervant Zorian, Juan Antonio Carballo. [doi]
• Design for Testability: The Path to Deep SubmicronThomas W. Williams. [doi]
• TTEP Introduction [doi]
• Robust Built-In Test of RF ICs Using Envelope DetectorsDonghoon Han, Abhijit Chatterjee. 2-7 [doi]
• Delay Defect Characterization Using Low Voltage TestHaihua Yan, Adit D. Singh, Gefu Xu. 8-13 [doi]
• Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost TesterShalabh Goyal, Michael Purtell. 14-17 [doi]
• IDDQ Testing Method using a Scan Pattern for Production TestingJunichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka. 18-21 [doi]
• A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron ChipsAjoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel. 22-27 [doi]
• An Efficient System-Level to RTL Verification Framework for Computation-Intensive ApplicationsNikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee. 28-33 [doi]
• Block-based Schema-driven Assertion Generation for Functional VerificationAmir Hekmatpour, Azadeh Salehi. 34-39 [doi]
• A Framework for Automatic Assembly Program Generator (A:::2:::PG) for Verification and Testing of Processor CoresK. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil. 40-45 [doi]
• The Automatic Generation of Basis Set of Path for Path TestingGuangmei Zhang, Chen Rui, Xiaowei Li, Han Congying. 46-51 [doi]
• Optimal Schemes for ADC BIST Based on HistogramYong-sheng Wang, Jinxiang Wang, Feng-chang Lai, Yizheng Ye. 52-57 [doi]
• A 5 Gbps Wafer-Level TesterA. M. Majid, David C. Keezer, J. V. Karia. 58-63 [doi]
• Low-cost Production Test of BER for Wireless ReceiversAchintya Halder, Abhijit Chatterjee. 64-69 [doi]
• Design of a CMOS Operational Amplifier for Extreme-Voltage Stress TestShaolei Quan, Qiang Qiang, Chin-Long Wey. 70-75 [doi]
• New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft ErrorsDaniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel. 76-81 [doi]
• A State Machine for Detecting C/C++ Memory FaultsGuangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong. 82-87 [doi]
• On-Line Testing of Digital Circuits for n-Detect and Bridging Fault ModelsS. Biswas, P. Srikanth, R. Jha, S. Mukhopadhyay, A. Patra, D. Sarkar. 88-93 [doi]
• Boundary Value Testing based on UML ModelsPhilip Samuel, Rajib Mall. 94-99 [doi]
• Random Jitter Testing Using Low Tap-Count Delay LinesJiun-Lang Huang. 100-105 [doi]
• Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia PrincipleMing Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu. 106-111 [doi]
• A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary InterconnectsWichian Sirisaengtaksin, Sandeep K. Gupta. 112-119 [doi]
• Non-robust Test Generation for Crosstalk-Induced Delay FaultsPei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li. 120-125 [doi]
• Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BISTDong Xiang, Ming-Jing Chen, Hideo Fujiwara. 126-131 [doi]
• Circuit Independent Weighted Pseudo-Random BIST Pattern GeneratorChaowen Yu, Sudhakar M. Reddy, Irith Pomeranz. 132-137 [doi]
• Low Transition LFSR for BIST-Based ApplicationsMohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed. 138-143 [doi]
• A BIST Scheme Based on Selecting State Generation of Folding CountersHuaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang. 144-149 [doi]
• Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive TestabilityTomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara. 150-155 [doi]
• Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test CompressionHiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi. 156-161 [doi]
• SOC Test Scheduling with Test Set Sharing and BroadcastingAnders Larsson, Erik Larsson, Petru Eles, Zebo Peng. 162-169 [doi]
• A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter VariationsAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy. 170-175 [doi]
• Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAMSaibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy. 176-181 [doi]
• Flash Memory Die Sort by a Sample Classification MethodYu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen. 182-187 [doi]
• Chip Identification using the Characteristic Dispersion of TransistorJunichi Hirase, Tatsuya Furukawa. 188-193 [doi]
• Untestable Multi-Cycle Path Delay Faults in Industrial DesignsManan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty. 194-201 [doi]
• Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch TransitionsNarendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz. 202-207 [doi]
• Selection of Paths for Delay TestingI-De Huang, Sandeep K. Gupta. 208-215 [doi]
• On Improving Defect Coverage of Stuck-at Fault TestsKohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy. 216-223 [doi]
• A Scan Matrix Design for Low Power Scan-Based TestShih-Ping Lin, Chung-Len Lee, Jwu E. Chen. 224-229 [doi]
• A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST ArchitectureYoubean Kim, Myung-Hoon Yang, Yong Lee 0002, Sungho Kang. 230-235 [doi]
• ISC: Reconfigurable Scan-Cell Architecture for Low Power TestingHadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi. 236-241 [doi]
• Partial Gating Optimization for Power Reduction During Test ApplicationMohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar. 242-247 [doi]
• Bridge Defect Diagnosis with Physical InformationWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy. 248-253 [doi]
• Design for Testability Based on Single-Port-Change Delay Testing for Data PathsYuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara. 254-259 [doi]
• A Class of Linear Space Compactors for Enhanced DiagnosticThomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja. 260-265 [doi]
• On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage TestingSandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker. 266-271 [doi]
• State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data SizeDong Hyun Baik, Kewal K. Saluja. 272-277 [doi]
• Enhancing Fault Simulation Performance by Dynamic Fault ClusteringShahrzad Mirkhani, Zainalabedin Navabi. 278-283 [doi]
• Cost Optimal Design of Nonlinear CA based PRPG for Test ApplicationsSukanta Das, Hafizur Rahaman, Biplab K. Sikdar. 284-287 [doi]
• An Effective Design for Hierarchical Test Generation Based on Strong TestabilityHideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara. 288-293 [doi]
• Concurrent Test GenerationVishwani D. Agrawal, Alok S. Doshi. 294-299 [doi]
• Novel Bi-partitioned Scan Architecture to Improve Transition Fault CoverageV. R. Devanathan. 300-305 [doi]
• A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault EfficiencyHiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara. 306-311 [doi]
• Achieving High Test Quality with Reduced Pin Count TestingJay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press. 312-317 [doi]
• Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-FlopsDong Xiang, Kaiwei Li, Hideo Fujiwara. 318-323 [doi]
• Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan TestingShih-Ping Lin, Chung-Len Lee, Jwu E. Chen. 324-329 [doi]
• Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection EfficiencySameer Goel, Rubin A. Parekhji. 330-336 [doi]
• Efficient Test Compaction for Pseudo-Random TestingSheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya. 337-342 [doi]
• Test Data Compression with Partial LFSR-ReseedingYu-Hsuan Fu, Sying-Jyan Wang. 343-347 [doi]
• CryptoScan: A Secured Scan Chain ArchitectureDebdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya. 348-353 [doi]
• Pseudo-Parity Testing with Testable DesignShiyi Xu. 354-359 [doi]
• Finite State Machine Synthesis for At-Speed Oscillation TestabilityKatherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen. 360-365 [doi]
• A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test ArchitectureTsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa. 366-371 [doi]
• Scan Data Volume Reduction Using Periodically Alterable MUXs DecompressorYinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra. 372-377 [doi]
• Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test RelaxationAiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait. 378-385 [doi]
• Low Power Test Compression Technique for Designs with Multiple Scan ChainYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura. 386-389 [doi]
• Threshold testing: Covering bridging and other realistic faultsZhigang Jiang, Sandeep K. Gupta. 390-397 [doi]
• Synthesis of Testable Finite State Machine Through DecompositionBiplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das. 398-403 [doi]
• Shannon Expansion Based Supply-Gated Logic for Improved Power and TestabilitySwaroop Ghosh, Swarup Bhunia, Kaushik Roy. 404-409 [doi]
• Flip-flop chaining architecture for power-efficient scan during test applicationShantanu Gupta, Tarang Vaish, Santanu Chattopadhyay. 410-413 [doi]
• A Unified Approach to Partial Scan Design using Genetic AlgorithmVarun Arora, Indranil Sengupta. 414-421 [doi]
• A Family of Logical Fault Models for Reversible CircuitsIlia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes. 422-427 [doi]
• Compressing Functional Tests for MicroprocessorsKedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil. 428-433 [doi]
• Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical ApproachZaid Al-Ars, Said Hamdioui, Jörg E. Vollrath. 434-439 [doi]
• Arithmetic Test Strategy for FFT ProcessorJi-Xue Xiao, Guang-Ju Chen, Yong-Le Xie. 440-443 [doi]
• Efficient Constraint Extraction for Template-Based Processor Self-Test GenerationKazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki. 444-449 [doi]
• IEEE Std 1500 Compliant Infrastructure forModular SOC TestingTom Waayers, Erik Jan Marinissen, Maurice Lousberg. 450 [doi]
• DFT for Low Cost SOC TestRubin A. Parekhji. 451 [doi]
• Managing Test and Repair of Embedded Memory Subsystem in SoCR. Chandramouli. 452 [doi]
• The Ultimate ChasePrabhu Krishnamurthy. 454 [doi]
• Defect-Oriented Test for Ultra-Low DPMVikram Iyengar, Phil Nigh. 455 [doi]
• Current Testing for Nanotechnologies: A Demystifying Application Perspective.Hans A. R. Manhaeve. 456 [doi]
• High Level Test Generation for Custom Hardware: An Industrial PerspectiveIndradeep Ghosh. 458 [doi]
• High Level Test Generation / SW based Embedded TestPraveen Parvathala. 459 [doi]
• Verification of Industrial Designs Using A Computing Grid With More than 100 NodesSubramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu. 460 [doi]
• Emerging Techniques for Test Data CompressionKedarnath J. Balakrishnan. 462 [doi]
• Improving Test Quality Using Test Data CompressionNilanjan Mukherjee. 463 [doi]
• Efficient Test Architecture based on Boundary Scan for Comprehensive System TestTapan J. Chakraborty. 464-465 [doi]
• Challenges in Next Generation Mixed-Signal IC Production TestingSasikumar Cherubal. 466 [doi]
• Practices in Testing of Mixed-Signal and RF SoCsSalem Abdennadher, Saghir A. Shaikh. 467 [doi]
• Challenges in High Speed Interface TestingSalem Abdennadher, Saghir A. Shaikh. 468 [doi]
• Practical Aspects of Delay Testing for Nanometer ChipsVivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman. 470 [doi]
• Limitation of structural scan delay testT. M. Mak. 471 [doi]
• Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVSTMohd Fairuz Zakaria, Zainal Abu Kassim, Melanie Po-Leen Ooi, Serge N. Demidenko. 472 [doi]