Table of Contents

• Fast OFDD based minimization of fixed polarity Reed-Muller expressionsRolf Drechsler, Bernd Becker, Michael Theobald. 2-7 [doi]
• Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mappingMarek A. Perkowski, Philip Ho. 8-13 [doi]
• Multilevel logic optimization of very high complexity circuitsLuc Burgun, N. Dictus, Alain Greiner, E. Prado Lopes, C. Sarwary. 14-19 [doi]
• Symbolic exploration of large circuits with enhanced forward/backward traversalsGianpiero Cabodi, Paolo Camurati, Stefano Quer. 22-27 [doi]
• Extended timing diagrams as a specification languageStefan Lenk. 28-33 [doi]
• Efficient algorithms for interface timing verificationTi-Yen Yen, Wayne Wolf, Albert E. Casavant, Alex Ishii. 34-39 [doi]
• A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuitsKerry S. Lowe, P. Glenn Gulak. 42-47 [doi]
• Layout optimization of planar CMOS cells regarding width-to-height trade-offMarkus Theißinger, Ronald D. Hindmarsh. 48-53 [doi]
• Automatic layout generation for CMOS analog transistorsH. Mathias, J. Berger-Toussan, Frédéric Gaffiot, L. Hébrard, Gilles Jacquemod, Michel Le Helley. 54-58 [doi]
• A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA sKlaus Buchenrieder, Christian Veith. 60-65 [doi]
• A performance evaluator for parameterized ASIC architecturesJie Gong, Daniel D. Gajski, Alex Nicolau. 66-71 [doi]
• Hardware-software-codesign of application specific microcontrollers with the ASM environmentA. Both, B. Biermann, R. Lerch, Yiannos Manoli, K. Sievert. 72-76 [doi]
• A hardware environment for prototyping and partitioning based on multiple FPGAsMarc Wendling, Wolfgang Rosenstiel. 77-82 [doi]
• GSA: scheduling and allocation using genetic algorithmAli Shahid, Muhammad S. T. Benten, Sadiq M. Sait. 84-89 [doi]
• OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programmingBirger Landwehr, Peter Marwedel, Rainer Dömer. 90-95 [doi]
• Parallel controller synthesis from a Petri net specificationKrzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul, Marian Adamski. 96-101 [doi]
• Parallel algorithms for the simulation of lossy transmission linesW. Rissiek, O. Rethmeier, H. Holzheuer. 104-109 [doi]
• Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpiceKonstantin O. Petrosjanc, Peter P. Maltcev. 110-115 [doi]
• TRICAP—a three dimensional capacitance solver for arbitrarily shaped conductors on printed circuit boards and VLSI interconnectionsMatthias Tröscher, Hans Hartmann, Georg Klein, Andreas Plettner. 116-121 [doi]
• Advanced simulation and modeling techniques for hardware quality verification of digital systemsS. Forno, Stephen Rochel. 122-127 [doi]
• OPERAS in a DSP CAD environmentJames B. Burr, Allen M. Peterson, Gerard K. Yeh, Kallol Kumar Bagchi. 130-135 [doi]
• Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effectsKaushik Roy, Sharat Prasad. 136-141 [doi]
• 100-hour design cycle: a test caseLoganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung. 144-149 [doi]
• A tool for processor instruction set designBruce K. Holmer. 150-155 [doi]
• Instruction set extraction from programmable structuresPeter Marwedel, Rainer Leupers. 156-161 [doi]
• Optimal equivalent circuits for interconnect delay calculations using momentsSudhakar Muddu, Andrew B. Kahng. 164-169 [doi]
• Efficient linear circuit analysis by Pade´ approximation via the Lanczos processPeter Feldmann, Roland W. Freund. 170-175 [doi]
• Multilevel generalization of relaxation algorithms for circuit simulationVladimir B. Dmitriyev-Zdorov. 176-181 [doi]
• MOS VLSI circuit simulation by hardware accelerator using semi-natural modelsVictor V. Denisenko. 182-186 [doi]
• A flexible access control mechanism for CAD frameworksA. J. van der Hoeven, K. Olav ten Bosch, Rene van Leuken, Pieter van der Wolf. 188-193 [doi]
• A tightly coupled approach to design and data managementFlávio Rech Wagner, Lia Goldstein Golendziner, Miguel Rodrigues Fornari. 194-199 [doi]
• Integrating CAD tools into a framework environment using a flexible and adaptable procedural interfaceNick Filer, Michael Brown, Zahir Moosa. 200-205 [doi]
• Design tool encapsulation—all problems solved?Olav Schettler. 206-211 [doi]
• A binary-constraint search algorithm for minimizing hardware during hardware/software partitioningFrank Vahid, Daniel D. Gajski, Jie Gong. 214-219 [doi]
• A method for partitioning UNITY language in hardware and softwareXun Xiong, Edna Barros, Wolfgang Rosenstiel. 220-225 [doi]
• Hardware/software partitioning and minimizing memory interface trafficAxel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen. 226-231 [doi]
• Reliability study of combinatorial circuitsEdgar Holmann, Ivan R. Linscott, G. Leonard Tyler. 234-239 [doi]
• Test pattern generation hardware motivated by pseudo-exhaustive test techniquesArno Kunzmann. 240-245 [doi]
• An experimental analysis of the effectiveness of the circular self-test path techniquePaolo Prinetto, Fulvio Corno, Matteo Sonza Reorda. 246-251 [doi]
• Design automation of self checking circuitsSayed Mohammad Kia, Sri Parameswaran. 252-257 [doi]
• An architecture-independent approach to FPGA routing based on multi-weighted graphsMichael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins. 259-264 [doi]
• Algorithms for a switch module routing problemShashidhar Thakur, D. F. Wong, S. Muthukrishnan. 265-270 [doi]
• A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitionsRoman Kuznar, Baldomir Zajc, Franc Brglez. 271-276 [doi]
• A delay driven FPGA placement algorithmSrilata Raman, C. L. Liu, Larry G. Jones. 277-282 [doi]
• Formal verification of pipeline conflicts in RISC processorsRamayya Kumar, Sofiène Tahar. 284-289 [doi]
• An automatically verified generalized multifunction arithmetic pipelineMatthias Mutz. 290-295 [doi]
• Formal specification and simulation of instruction-level parallelismEdwin A. Harcourt, Jon Mauney, Todd A. Cook. 296-301 [doi]
• An efficient verification algorithm for parallel controllersKrzysztof Bilinski, Erik L. Dagless, Jonathan Saul, Janusz Szajna. 302-307 [doi]
• Tests for path delay faults vs. tests for gate delay faults: how different they areAndrzej Krasniewski, Leszek B. Wronski. 310-315 [doi]
• RESIST: a recursive test pattern generation algorithm for path delay faultsKarl Fuchs, Michael Pabst, Torsten Rössel. 316-321 [doi]
• BiTeS: a BDD based test pattern generator for strong robust path delay faultsRolf Drechsler. 322-327 [doi]
• Testing redundant asynchronous circuits by variable phase splittingLuciano Lavagno, Antonio Lioy, Michael Kishinevsky. 328-333 [doi]
• Re-engineering hardware specifications by exploiting design semanticsSalvador Mir, Nick Filer. 336-341 [doi]
• The use of semantic information for control of a complex routing toolMichael Brown, Nick Filer, Zahir Moosa. 342-347 [doi]
• A new knowledge-based design manager assistant for CAD frameworksFélix Moreno, Juan M. Meneses. 348-353 [doi]
• The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithmChris J. Rousse, Alison J. Carter. 354-359 [doi]
• Compiled-code-based simulation with timing verificationWinfried Hahn, Andreas Hagerer, C. Herrmann. 362-367 [doi]
• A portable and extendible testbed for distributed logic simulationPeter Luksch. 368-373 [doi]
• Gate-level timing verification using waveform narrowingJindrich Zejda, Eduard Cerny. 374-379 [doi]
• Exact path sensitization in timing analysisR. Peset Llopis. 380-385 [doi]
• A new power estimation technique with application to decomposition of Boolean functions for low powerPeter H. Schneider, Kurt Antreich, Ulf Schlichtmann. 388-393 [doi]
• A new technique for exploiting regularity in data path synthesisC. Y. Roger Chen, Mohammed Aloqeely. 394-399 [doi]
• A component selection algorithm for high-performance pipelinesSmita Bakshi, Daniel D. Gajski. 400-405 [doi]
• Fast simulation method for the detection of reflection—and crosstalk effects during the design of complex printed circuit boardsE. Griese, J. Schrage, M. Vogt. 408-413 [doi]
• Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-WorkbenchStefan Öing, Werner John. 414-419 [doi]
• Overall thermal simulation of electronic equipmentJean-Louis Blanchard, Jean-Michel Morelle. 420-425 [doi]
• A macro-cell global router based on two genetic algorithmsHenrik Esbensen. 428-433 [doi]
• An appreciation of simulated annealing to maze routingZahir Moosa, Michael Brown, Douglas Edwards. 434-439 [doi]
• Planar-DME: improved planar zero-skew clock routing with minimum pathlength delayChung-Wen Albert Tsao, Andrew B. Kahng. 440-445 [doi]
• A general state graph transformation framework for asynchronous synthesisBill Lin, Chantal Ykman-Couvreur, Peter Vanbekbergen. 448-453 [doi]
• Evaluation of function blocks for asynchronous designChristian D. Nielsen. 454-459 [doi]
• Application-independent hierarchical synthesis methodology for analogue circuitsReimund Wittmann, Bedrich J. Hosticka, Michael Schanz, Werner Schardein, Stefan Kern, Reinhold Vahrmann. 466-471 [doi]
• Generating VHDL models from natural language descriptionsWalling R. Cyre, Jim Armstrong, M. Manek-Honcharik, Alexander J. Honcharik. 474-479 [doi]
• Non-reversible VHDL source-source encryptionKevin O Brien, Serge Maginot. 480-485 [doi]
• Modeling shared variables in VHDLJan Madsen, Jens P. Brage. 486-491 [doi]
• A VHDL-based bus model for multi-PCB system designJari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuominen. 492-497 [doi]
• The semantics of behavioral VHDL 93 descriptionsWolfgang Müller, Egon Börger, Uwe Glässer. 500-505 [doi]
• A process algebra interpretation of a verification oriented overlanguage of VHDLCatherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto. 506-511 [doi]
• Proof theory and a validation condition generator for VHDLLuis Sánchez Fernández, Peter T. Breuer, Carlos Delgado Kloos. 512-517 [doi]
• Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis toolsJuan Carlos Calderón, Enric Corominas, José M. Tapia, Luis París. 520-525 [doi]
• VHDL and cyclic corrector codesFrance Mendez. 526-531 [doi]
• Generating compilers for generated datapathsMichael Held, Manfred Glesner. 532-537 [doi]
• Synthesis of VHDL concurrent processesPetru Eles, Marius Minea, Krzysztof Kuchcinski, Zebo Peng. 540-545 [doi]
• Scheduling of behavioral VHDL by retiming techniquesNorbert Wehn, J. Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, S. Rumler. 546-551 [doi]
• A transformation for integrating VHDL behavioral specification with synthesis and software generationFrank Vahid, Daniel D. Gajski, Sanjiv Narayan. 552-557 [doi]
• Formal verification of behavioral VHDL specifications: a case studyFelix Nicoli, Laurence Pierre. 560-565 [doi]
• (V)HDL-based verification of heterogeneous synchronous/asynchronous systemsHans Eveking. 566-571 [doi]
• Petri nets as intermediate representation between VHDL and symbolic transition systemsGert Döhmen. 572-577 [doi]
• Computing binary decision diagrams for VHDL data typesRonald Herrmann, Hergen Pargmann. 578-583 [doi]
• Static analysis for VHDL model evaluationMario Stefanoni. 586-591 [doi]
• Automotive databus simulation using VHDLKaren Hale. 592-597 [doi]
• Distributed simulation for structural VHDL netlistsDavid B. Bernstein, Werner van Almsick, Wilfried Daehn. 598-603 [doi]
• A new flexible VHDL simulatorArlet Ottens, Henk Corporaal, Wilco Van Hoogstraeten. 604-609 [doi]
• The role of VHDL within the TOSCA hardware/software codesign frameworkDonatella Sciuto, Stefano Antoniazzi, Alessandro Balboni, William Fornaciari. 612-617 [doi]
• Timing preserving interface transformations for the synthesis of behavioral VHDLP. Gutberlet, Wolfgang Rosenstiel. 618-623 [doi]
• Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operationsWolfgang Ecker, Manfred Glesner, Andreas Vombach. 624-629 [doi]
• Speeding up test pattern generation from behavioral VHDL descriptions containing several processesLoïc Vandeventer, Jean François Santucci. 632-637 [doi]
• Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructsLoïc Vandeventer, Jean François Santucci. 638-643 [doi]
• Testability analysis and improvement from VHDL behavioral specificationsXinli Gu, Krzysztof Kuchcinski, Zebo Peng. 644-649 [doi]
• VHDL switch level fault simulationChristopher A. Ryan, Joseph G. Tront. 650-655 [doi]
• ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon CodecKoen Van Nieuwenhove, Kjell Cools, D. Devisch, Ivo Bolsens, Serge Vernalde, Kim Chansik, R. B. W. Lee, Oh Younguk. 658-663 [doi]
• A VHDL-based design methodology: the design experience of a high performance ASIC chipMaurizio Valle, Daniele D. Caviglia, Marco Cornero, Giovanni Nateri, Luciano Briozzo. 664-669 [doi]
• SYNOPA: an automated synthesizer for CMOS operational amplifiersDaniel Clavelier, Bernard Hennion, Christopher Nilson. 670-675 [doi]
• Using C to write portable CMOS VLSI module generatorsAlain Greiner, Frédéric Pétrot. 676-681 [doi]
• Rapid prototyping for DSP circuits using high level design toolsStefan Tamme. 682-687 [doi]
• CAD education and science in Ukraine after PerestroikaAlexander Y. Tetelbaum. 688-693 [doi]