Proof theory and a validation condition generator for VHDL

Luis Sánchez Fernández, Peter T. Breuer, Carlos Delgado Kloos. Proof theory and a validation condition generator for VHDL. In Jean Mermet, editor, Proceedings EURO-DAC 94, European Design Automation Conference, Grenoble, France, September 19-22, 1994. pages 512-517, IEEE Computer Society, 1994. [doi]

Abstract

Abstract is missing.