Table of Contents

• Fault tolerant Four-State Logic by using Self-Healing CellsThomas Panhofer, Werner Friesenbichler, Martin Delvai. 1-6 [doi]
• Probabilistic error propagation in logic circuits using the Boolean difference calculusNasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram. 7-13 [doi]
• A novel, highly SEU tolerant digital circuit design approachRajesh Garg, Sunil P. Khatri. 14-20 [doi]
• Power-state-aware buffered tree constructionIris Hui-Ru Jiang, Ming-Hua Wu. 21-26 [doi]
• A parallel Steiner tree heuristic for macro cell routingChristian Fobel, Gary Grewal. 27-33 [doi]
• Configurable rectilinear Steiner tree construction for SoC and nano technologiesIris Hui-Ru Jiang, Yen-Ting Yu. 34-39 [doi]
• Improving SAT-based Combinational Equivalence Checking through circuit preprocessingFabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes. 40-45 [doi]
• Ant Colony Optimization directed program abstraction for software bounded model checkingXueqi Cheng, Michael S. Hsiao. 46-51 [doi]
• Propositional approximations for bounded model checking of partial circuit designsBernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew D. T. Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer. 52-59 [doi]
• Energy-precision tradeoffs in mobile Graphics Processing UnitsJeff Pool, Anselmo Lastra, Montek Singh. 60-67 [doi]
• Dynamically reconfigurable soft output MIMO detectorPankaj Bhagawat, Rajballav Dash, Gwan Choi. 68-73 [doi]
• Applying speculation techniques to implement functional unitsAlberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado. 74-80 [doi]
• Accelerating search and recognition with a TCAM functional unitAtif Hashmi, Mikko Lipasti. 81-86 [doi]
• Improved combined binary/decimal fixed-point multipliersBrian J. Hickmann, Michael J. Schulte, Mark A. Erle. 87-94 [doi]
• Architecture implementation of an improved decimal CORDIC methodJosé Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno. 95-100 [doi]
• A study of reliability issues in clock distribution networksAida Todri, Malgorzata Marek-Sadowska. 101-106 [doi]
• Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlationsChunchen Liu, Junjie Su, Yiyu Shi. 107-113 [doi]
• Custom rotary clock routerVinayak Honkote, Baris Taskin. 114-119 [doi]
• Safe clocking register assignment in datapath synthesisKeisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki. 120-127 [doi]
• Gate planning during placement for gated clock networkWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. 128-133 [doi]
• Near-optimal oblivious routing on three-dimensional mesh networksRohit Sunkam Ramanujam, Bill Lin. 134-141 [doi]
• Design of application-specific 3D Networks-on-Chip architecturesShan Yan, Bill Lin. 142-149 [doi]
• Mathematical analysis of buffer sizing for Network-on-Chips under multimedia trafficAhmad Khonsari, Mohammad R. Aghajani, Arash Tavakkol, Mohammad Sadegh Talebi. 150-155 [doi]
• A resource efficient content inspection system for next generation Smart NICsKarthik Sabhanatarajan, Ann Gordon-Ross. 156-163 [doi]
• Contention-aware application mapping for Network-on-Chip communication architecturesChen-Ling Chou, Radu Marculescu. 164-169 [doi]
• Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilitiesKaijian Shi. 170-175 [doi]
• Adaptive SRAM memory for low power and high yieldBaker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham. 176-181 [doi]
• On-chip high performance signaling using passive compensationYulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng. 182-187 [doi]
• A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parametersMichael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann. 188-193 [doi]
• Characterization and design of sequential circuit elements to combat soft errorHamed Abrishami, Safar Hatami, Massoud Pedram. 194-199 [doi]
• Comparative analysis of NBTI effects on low power and high performance flip-flopsKrishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie. 200-205 [doi]
• In-field NoC-based SoC testing with distributed test vector storageJason D. Lee, Rabi N. Mahapatra. 206-211 [doi]
• Test-access mechanism optimization for core-based three-dimensional SOCsXiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie. 212-218 [doi]
• Characterization of granularity and redundancy for SRAMs for optimal yield-per-areaJae Chul Cha, Sandeep K. Gupta. 219-226 [doi]
• Dynamic test scheduling for analog circuits for improved test qualityEnder Yilmaz, Sule Ozev. 227-233 [doi]
• Test cost minimization through adaptive test developmentMingjing Chen, Alex Orailoglu. 234-239 [doi]
• Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGAYong Dou, Fei Xia, Xingming Zhou, Xuejun Yang. 240-247 [doi]
• A high-performance parallel CAVLC encoder on a fine-grained many-core systemZhibin Xiao, Bevan Baas. 248-254 [doi]
• Acceleration of a 3D target tracking algorithm using an application specific instruction set processorSebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois. 255-259 [doi]
• Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAsAmir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao. 260-265 [doi]
• Application Specific Instruction set processor specialized for block motion estimationMarc-Andre Daigneault, J. M. Pierre Langlois, Jean-Pierre David. 266-271 [doi]
• Prototyping a hybrid main memory using a virtual machine monitorDong Ye, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo. 272-279 [doi]
• Variation-aware thermal characterization and management of multi-core architecturesEren Kursun, Chen-Yong Cher. 280-285 [doi]
• Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspectiveVenkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai. 286-293 [doi]
• Analysis and minimization of practical energy in 45nm subthreshold logic circuitsDavid Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat. 294-300 [doi]
• Power-aware soft error hardening via selective voltage scalingKai-Chiang Wu, Diana Marculescu. 301-306 [doi]
• Reversi: Post-silicon validation system for modern microprocessorsIlya Wagner, Valeria Bertacco. 307-314 [doi]
• Digital filter synthesis considering multiple adder graphs for a coefficientJeong-Ho Han, In-Cheol Park. 315-320 [doi]
• A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communicationsAdnan Suleiman, Hani Saleh, Adel Hussein, David Akopian. 321-327 [doi]
• Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga. 328-333 [doi]
• Highly reliable A/D converter using analog votingAli Namazi, S. Askari, Mehrdad Nourani. 334-339 [doi]
• Hierarchical simulation-based verification of Anton, a special-purpose parallel machineJohn P. Grossman, John K. Salmon, Richard C. Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw. 340-347 [doi]
• Post-silicon verification for cache coherenceAndrew DeOrio, Adam Bauserman, Valeria Bertacco. 348-355 [doi]
• Acquiring an exhaustive, continuous and real-time trace from SoCsChristian Hochberger, Alexander Weiss. 356-362 [doi]
• CrashTest: A fast high-fidelity FPGA-based resiliency analysis frameworkAndrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin. 363-370 [doi]
• Exploiting spare resources of in-order SMT processors executing hard real-time threadsJörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer. 371-376 [doi]
• Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-designCarsten Gremzow. 377-383 [doi]
• A simple latency tolerant processorSatyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song. 384-389 [doi]
• Low-cost open-page prefetch scheduling in chip multiprocessorsMarius Grannæs, Magnus Jahre, Lasse Natvig. 390-396 [doi]
• Simulation points for SPEC CPU 2006Arun A. Nair, Lizy K. John. 397-403 [doi]
• Synthesis of parallel prefix adders considering switching activitiesTaeko Matsunaga, Shinji Kimura, Yusuke Matsunaga. 404-409 [doi]
• Conversion driven design of binary to mixed radix circuitsAshur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev. 410-415 [doi]
• Systematic design of high-radix Montgomery multipliers for RSA processorsAtsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh. 416-421 [doi]
• An improved micro-architecture for function approximation using piecewise quadratic interpolationShai Erez, Guy Even. 422-426 [doi]
• A floating-point fused dot-product unitHani Saleh, Earl E. Swartzlander Jr.. 427-431 [doi]
• Chip level thermal profile estimation using on-chip temperature sensorsYufu Zhang, Ankur Srivastava, Mohamed M. Zahran. 432-437 [doi]
• Early stage FPGA interconnect leakage power estimationShilpa Bhoj, Dinesh Bhatia. 438-443 [doi]
• Modeling and analysis of non-rectangular transistors caused by lithographic distortionsAswin Sreedhar, Sandip Kundu. 444-449 [doi]
• A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitionsDimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos. 450-456 [doi]
• Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yieldAditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang. 457-462 [doi]
• Frequency and voltage planning for multi-core processors under thermal constraintsMichael Kadin, Sherief Reda. 463-470 [doi]
• Understanding performance, power and energy behavior in asymmetric multiprocessorsNagesh B. Lakshminarayana, Hyesoon Kim. 471-477 [doi]
• Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip MultiprocessorMichael Gschwind. 478-485 [doi]
• The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networksReza Sabbaghi-Nadooshan, Mehdi Modarressi, Hamid Sarbazi-Azad. 486-490 [doi]
• Design and evaluation of an optical CPU-DRAM interconnectAmit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew Farrens, Venkatesh Akella. 492-497 [doi]
• Leveraging speculative architectures for run-time program validationJuan Carlos Martinez Santos, Yunsi Fei. 498-505 [doi]
• Bridging the gap between nanomagnetic devices and circuitsMichael T. Niemier, Xiaobo Sharon Hu, Aaron Dingler, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod. 506-513 [doi]
• Techniques for increasing effective data bandwidthChristopher Nitta, Matthew Farrens. 514-519 [doi]
• RMA: A Read Miss-Based Spin-Down Algorithm using an NV cacheHyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Kim, Seungryoul Maeng. 520-525 [doi]
• Combined interpolation architecture for soft-decision decoding of Reed-Solomon codesJiangli Zhu, Xinmiao Zhang, Zhongfeng Wang. 526-531 [doi]
• Timing analysis considering IR drop waveforms in power gating designsShih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska. 532-537 [doi]
• A dynamic accuracy-refinement approach to timing-driven technology mappingSz-Cheng Huang, Jie-Hong Roland Jiang. 538-543 [doi]
• Modeling and reduction of complex timing constraints in high performance digital circuitsVeerapaneni Nagbhushan, C. Y. Roger Chen. 544-550 [doi]
• SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvementAnuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi. 551-556 [doi]
• Is there always performance overhead for regular fabric?Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz. 557-562 [doi]
• Adaptive techniques for leakage power management in L2 cache peripheral circuitsHouman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot. 563-569 [doi]
• Energy-aware opcode designBalaji V. Iyer, Jason A. Poovey, Thomas M. Conte. 570-576 [doi]
• Making register file resistant to power analysis attacksShuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhijie Jerry Shi. 577-582 [doi]
• Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloadsShrirang M. Yardi, Michael S. Hsiao. 583-590 [doi]
• Suitable cache organizations for a novel biomedical implant processorChristos Strydis. 591-598 [doi]
• Issue system protection mechanismsPedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera. 599-604 [doi]
• Power switch characterization for fine-grained dynamic voltage scalingLiang Di, Mateja Putic, John Lach, Benton H. Calhoun. 605-611 [doi]
• A fine-grain dynamic sleep control scheme in MIPS R3000Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. 612-617 [doi]
• Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEWHao Xu, Ranga Vemuri, Wen-Ben Jone. 618-625 [doi]
• Energy-delay tradeoffs in 32-bit static shifter designsSteven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil. 626-632 [doi]
• Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systemsBaoxian Zhao, Hakan Aydin, Dakai Zhu. 633-639 [doi]
• Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuitsFeng Shi. 640-645 [doi]
• Router and cell library co-development for improving redundant via insertion at pinsWei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin. 646-651 [doi]
• ECO-Map: Technology remapping for post-mask ECO using simulated annealingNilesh A. Modi, Malgorzata Marek-Sadowska. 652-657 [doi]
• Global bus route optimization with application to microarchitectural design explorationDae-Hyun Kim, Sung Kyu Lim. 658-663 [doi]
• Fast arbiters for on-chip network switchesGiorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos. 664-670 [doi]
• Re-examining cache replacement policiesJason Zebchuk, Srihari Makineni, Donald Newell. 671-678 [doi]
• Two dimensional highly associative level-two cache designChuanjun Zhang, Bing Xue. 679-684 [doi]
• Exploiting producer patterns and L2 cache for timely dependence-based prefetchingChungsoo Lim, Gregory T. Byrd. 685-692 [doi]
• Ring data location prediction scheme for Non-Uniform Cache ArchitecturesSayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin. 693-698 [doi]
• ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuitsHouman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum. 699-706 [doi]