Dominik Kasprowicz - researchr alias

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Viewing Publication 1 - 11 from 11

2019

Table-Based Model of a Dual-Gate Transistor for Statistical Circuit SimulationDominik Kasprowicz. tcad, 38(8):1493-1500, 2019. [doi]

Semiconductor Device Parameter Extraction Based on I-V Measurements and SimulationDominik Kasprowicz. mixdes 2019: 321-326 [doi]

2017

Variability-aware table-based DC model of a dual-gate transistorDominik Kasprowicz. mixdes 2017: 154-158 [doi]

2015

Channel charge model of a dual-gate junctionless transistorDominik Kasprowicz. mixdes 2015: 216-221 [doi]

2014

Methods for automated detection of plagiarism in integrated-circuit layoutsDominik Kasprowicz, Hilekaan Wada. mj, 45(9):1212-1219, 2014. [doi]

2013

VeSFET as an analog-circuit componentDominik Kasprowicz, Bartosz Swacha. ddecs 2013: 199-204 [doi]

Computer-aided detection of plagiarism in integrated-circuit layoutsDominik Kasprowicz, Hilekaan Wada. mixdes 2013: 213-217 [doi]

2009

Adder Circuits with Transistors using Independently Controlled GatesMarcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel. iscas 2009: 449-452 [doi]

2008

Is there always performance overhead for regular fabric?Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz. iccd 2008: 557-562 [doi]

2003

Improvement of integrated circuit testing reliability by using the defect based approachDominik Kasprowicz, Witold A. Pleskacz. mr, 43(6):945-953, 2003. [doi]

2001

CMOS Standard Cells Characterization for Defect Based TestingWitold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz. dft 2001: 384 [doi]

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