Abstract is missing.
- Foreword to the 16th IEEE DDECS Symposium [doi]
- Hardware-Software Co-Visualization: Developing systems in the holodeckRolf Drechsler, Mathias Soeken. 1-4 [doi]
- Approximate computing for energy-efficient error-resilient multimedia systemsKaushik Roy. 5-6 [doi]
- Creating options for 3D-SIC testingErik Jan Marinissen. 7 [doi]
- Interpolation-based model checking for efficient incremental analysis of softwareGrigory Fedyukovich, Antti E. J. Hyvarinen, Natasha Sharygina. 8-9 [doi]
- Cross-layer resilient system designMehdi Baradaran Tahoori. 10 [doi]
- Hardware acceleration in computer networksJan Korenek. 11 [doi]
- Fault-based attacks on cryptographic hardwareIlia Polian, Martin Kreuzer. 12-17 [doi]
- Exploring processor parallelism: Estimation methods and optimization strategiesRoel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal. 18-23 [doi]
- On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systemsJosef Strnadel. 24-29 [doi]
- m) multipliers dedicated for cryptographic applicationsDanuta Pamula, Edward Hrynkiewicz. 30-35 [doi]
- On the on-line functional test of the Reorder Buffer memory in superscalar processorsS. Di Carlo, E. Sanchez, Matteo Sonza Reorda. 36-41 [doi]
- Fault collapsing of multi-conditional faultsRene Krenz-Baath, Andreas Glowatz, Friedrich Hapke. 42-47 [doi]
- Efficient automated speedpath debuggingMehdi Dehbashi, Görschwin Fey. 48-53 [doi]
- A static analysis approach to data race detection in SystemC designsMikhail J. Moiseev, Mikhail Glukhikh, Alexey V. Zakharov, Harald Richter. 54-59 [doi]
- Debugging HDL designs based on functional equivalences with high-level specificationsAlexander Finder, Jan-Philipp Witte, Görschwin Fey. 60-65 [doi]
- Design of stochastic Viterbi decoders for convolutional codesTe-Hsuan Chen, John P. Hayes. 66-71 [doi]
- 10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technologyAtef Mohamed, Hong Chen, Horst Zimmermann. 72-75 [doi]
- Ultra-high bandwidth fully-differential three-stage operational amplifiers in 40nm digital CMOSHong Chen, Vladimir Milovanovic, Dario Giotta, Horst Zimmermann. 76-81 [doi]
- A GHz full-division-range programmable divider with output duty-cycle improvedYu-lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang. 82-85 [doi]
- An area efficient hardware architecture design for H.264/AVC intra prediction reconstruction path based on partial reconfigurationMilica Orlandic, Kjetil Svarstad. 86-91 [doi]
- Automatic synthesis of small AdaBoost classifier in FPGAFilip Kadlcek, Otto Fucík. 92-97 [doi]
- A low jitter delay-locked-loop applied for DDR4Yo-Hao Tu, Kuo-Hsing Cheng, Hsiang-Yun Wei, Hong-Yi Huang. 98-101 [doi]
- Power analysis methodology for secure circuitsKamil Gomina, Jean-Baptiste Rigaud, Philippe Gendrier, Philippe Candelier, Assia Tria. 102-107 [doi]
- Towards hardware architecture for memory efficient IPv4/IPv6 Lookup in 100 Gbps networksJirí Matousek, Martin Skacan, Jan Korenek. 108-111 [doi]
- Extensible open-source framework for translating RTL VHDL IP cores to SystemCSyed Saif Abrar, Maksim Jenihhin, Jaan Raik. 112-115 [doi]
- Multiobjective evolution of approximate multiple constant multipliersJiri Petrlik, Lukás Sekanina. 116-119 [doi]
- Hardware architecture for the fast pattern matchingJan Kastil, Vlastimil Kosar, Jan Korenek. 120-123 [doi]
- Digital methods of offset compensation in 90nm CMOS operational amplifiersGabriel Nagy, Daniel Arbet, Viera Stopjaková. 124-127 [doi]
- Frequency injection attack on a random number generatorSimona Buchovecka, Josef Hlavác. 128-130 [doi]
- Embedded microcontroller system for PilsenCUBE picosatellitePavel Fiala, Ales Vobornik. 131-134 [doi]
- Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devicesAmir Hasanbegovic, Snorre Aunet. 135-140 [doi]
- Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agentsMojtaba Valinataj, Pasi Liljeberg, Juha Plosila. 141-146 [doi]
- A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0Julien Saade, Frédéric Pétrot, Andre Picco, Joel Huloux, Abdelaziz Goulahsen. 147-152 [doi]
- A Multi-Credit Flow Control scheme for asynchronous NoCsSyed Rameez Naqvi, Robert Najvirt, Andreas Steininger. 153-158 [doi]
- An indirect technique for estimating reliability of analog and mixed-signal systems during operational lifeMuhammad Aamir Khan, Hans G. Kerkhoff. 159-164 [doi]
- Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologiesKrzysztof Siwiec, Aleksander Koter, Witold A. Pleskacz. 165-169 [doi]
- Numerical method for DC fault analysis simplification and simulation time reductionJuraj Brenkus, Viera Stopjaková, Gábor Gyepes. 170-174 [doi]
- Relocation of reconfigurable modules on Xilinx FPGATomas Drahonovsky, Martin Rozkovec, Ondrej Novák. 175-180 [doi]
- On performance estimation of a scalable VLIW soft-core in XILINX FPGAsPetr Pfeifer, Zdenek Plíva, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus. 181-186 [doi]
- On the feasibility of combining on-line-test and self repair for logic circuitsTobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus. 187-192 [doi]
- Yield-oriented energy and performance model for subthreshold circuits with Vth variationsHans Kristian Otnes Berge, Snorre Aunet. 193-198 [doi]
- VeSFET as an analog-circuit componentDominik Kasprowicz, Bartosz Swacha. 199-204 [doi]
- Efficient mixture preparation on digital microfluidic biochipsSrijan Kumar, Sudip Roy, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. 205-210 [doi]
- Composing data-driven circuits using handshake in the clock-synchronous domainJaroslav Sykora. 211-214 [doi]
- A don't care identification method for test compactionHiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura. 215-218 [doi]
- Test pattern decompression in parallel scan chain architectureMartin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec. 219-223 [doi]
- Indoor energy harvesting using photovoltaic cell for battery rechargingHong-Yi Huang, Chinet Otic Mocorro, Julyver Pinaso, Kuo-Hsing Cheng. 224-227 [doi]
- Noise and linearity analysis of a frequency to voltage converterJørgen Andreas Michaelsen, Dag T. Wisland. 228-231 [doi]
- Energy-aware software development for embedded systems in HW/SW co-designPaul Ehrlich, Stephan Radke. 232-235 [doi]
- External capacitorless low dropout linear regulator using cascode structureHong-Yi Huang, Cheng-Yu Chen, Kuo-Hsing Cheng. 236-239 [doi]
- FPGA based time-of-flight 3D camera characterization systemJohannes Seiter, Michael Hofbauer, Milos Davidovic, Horst Zimmermann. 240-245 [doi]
- Error resilient OBDDsAnna Bernasconi, Valentina Ciriani, Lorenzo Lago. 246-249 [doi]
- Design of an S-band 0.35 µm AlGaN/GaN LNA using cascode topologyH. L. Kao, C.-S. Yeh, C. L. Cho, B. W. Wang, P. C. Lee, B. H. Wei, H. C. Chiu. 250-253 [doi]
- Assertion based verification using PSL-like properties in HaskellBahram N. Uchevler, Kjetil Svarstad. 254-257 [doi]
- Reliability-aware cross-layer custom instruction screeningBahareh J. Farahani, Ali Azarpeyvand, Saeed Safari, Seid Mehdi Fakhraie. 258-262 [doi]
- Efficiency of oscillation-based BIST in 90nm CMOS active analog filtersDaniel Arbet, Gabriel Nagy, Viera Stopjaková, Gábor Gyepes. 263-266 [doi]
- FPGA architecture for fast floating point matrix inversion using uni-dimensional systolic array based structureOndrej Hnilicka. 267-270 [doi]
- Redundancy algorithm for embedded memories with block-based architectureStefan Kristofik, Elena Gramatová. 271-274 [doi]
- Analysis and comparison of functional verification and ATPG for testing design reliabilityMarcela Simková, Zdenek Kotásek, Cristiana Bolchini. 275-278 [doi]
- Fault-Tolerant Reconfigurable Low-Power pseudoRandom number GeneratorVladimir Petrovic, Zoran Stamenkovic, Mile K. Stojcev, Tatjana Nikolic, Goran S. Jovanovic. 279-282 [doi]
- A new method for correcting time and soft errors in combinational circuitsEgor S. Sogomonyan, Stefan Weidling, Michael Gössel. 283-286 [doi]
- MBIST for LEON3 processor core cacheAndrej Kincel, Marcel Baláz. 287-288 [doi]
- Fault tolerant CAN bus control system implemented into FPGAKarel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek. 289-292 [doi]
- Improved design of the uninterruptable power supply unit for powering of network devicesMartin Pospisilik, Petr Neumann. 293-294 [doi]
- Hybrid Mesh-Ring wireless NoC for multi-core systemMohamed A. Wanas, Mohamed A. Abd El ghany, Klaus Hofmann. 295-296 [doi]
- Novel model calibration method based on differential evolution used for SCR model fittingTomas Napravnik, Premysl Ziska, Jiri Jakovenko. 297-298 [doi]