Abstract is missing.
- A distributed controller for system level integrationM. Vashi, Vijay K. Raj, Hee Yong Youn. 2-5 [doi]
- Optimizing cyclic data-flow graphs via associativityLiang-Fang Chao. 6-10 [doi]
- Abstraction of data path registers for multilevel verification of large circuitsYatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell. 11-14 [doi]
- Automated system partitioning for synthesis of multi-chip modulesRaghava V. Cherabuddi, Magdy A. Bayoumi. 15-20 [doi]
- Floorplan area optimization using genetic algorithmsMaurizio Rebaudengo, Matteo Sonza Reorda. 22-25 [doi]
- Floorplanning for mixed macro block and standard cell designsArun Shanbhag, Srinivasa R. Danda, Naveed A. Sherwani. 26-29 [doi]
- Convergence analyses of simulated evolution algorithmsChi-Yu Mao, Yu Hen Hu. 30-33 [doi]
- Estimating the storage requirements of the rectangular and L-shaped corner stitching data structuresDinesh P. Mehta. 34-37 [doi]
- A new systolic architecture for pipeline prime factor DFT-algorithmStanislav G. Sedukhin. 40-45 [doi]
- The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applicationsJermy C. Smith, Fred J. Taylor. 46-49 [doi]
- Structural fault tolerance in VLSI-based systemsHung-Kuei Ku, John P. Hayes. 50-55 [doi]
- An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processorsChin-Chien Sha, R. W. Leavene. 56-61 [doi]
- Generalized segmented channel routingV. Shankar, Dinesh Bhatia. 64-69 [doi]
- On computational complexity of a detailed routing problem in two dimensional FPGAsYu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska. 70-75 [doi]
- Mathematical model for routability analysis of FPGAsDinesh Bhatia, Amit Chowdhary, Spyros Tragoudas. 76-79 [doi]
- An optimal algorithm for maximum two planar subset problem [VLSI layout]Anand Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani. 80-85 [doi]
- A performance driven logic synthesis system using delay estimatorYulin Chen, Wei Kang Tsai, Fadi J. Kurdahi, Tzong-Dar Her, Champaka Ramachandran. 88-92 [doi]
- Symbolic traversals of data paths with auxiliary variablesGianpiero Cabodi, Paolo Camurati, Stefano Quer. 93-96 [doi]
- FPGA-based synthesis of FSMs through decompositionW. L. Yang, Robert Michael Owens, Mary Jane Irwin. 97-100 [doi]
- Communication based multilevel synthesis for multi-output Boolean functionsPaul Molitor, Christoph Scholl. 101-104 [doi]
- A new scheme to compute variable orders for binary decision diagramsJawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell. 105-108 [doi]
- Design of a package for a high-speed processor made with yield-limited technologyAtul Garg, James Loy, Hans J. Greub, John F. McDonald. 110-113 [doi]
- A flow based approach to the pin redistribution problem for multi-chip modulesDouglas Chang, Teofilo F. Gonzalez, Oscar H. Ibarra. 114-119 [doi]
- Wiring pitch integrates MCM design domainsJames Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald. 120-123 [doi]
- A VLSI CAM-based flexible oblivious router for multiprocessor interconnection networksJosé G. Delgado-Frias, Rovy Sze, Douglas H. Summerville, Valentine C. Aikens II. 124-129 [doi]
- Design of transport triggered architecturesHenk Corporaal. 130-135 [doi]
- ASIC design for robust signal and image processingRichard R. Schultz, H. M. Zeyedt, Robert L. Stevenson, R. J. Minniti, C. H. Bernstein. 138-143 [doi]
- VLSI implementation of CORDIC angle unitsJeong-A. Lee, M. Ahmad. 144-149 [doi]
- Mapping tensor products onto VLSI networks with reduced I/OAyman Elnaggar, Hussein M. Alnuweiri, Mabo Robert Ito. 150-155 [doi]
- A gridless multi-layer area routerNaresh Sehgal, C. Y. Roger Chen, John M. Acken. 158-161 [doi]
- Routability crossing distribution and floating terminal assignment of T-type junction regionJin-Tai Yan, Pei-Yung Hsiao. 162-165 [doi]
- Simulated annealing based yield enhancement of layoutsRamesh Karri, Alex Orailoglu. 166-169 [doi]
- An efficient algorithm for the realizability analysis of signal transition graphsHon Fung Li, S. C. Leung. 174-179 [doi]
- Distributed data-path synthesis on a network of workstationsMehmet Emin Dalkiliç, Vijay Pitchumani. 180-183 [doi]
- Basic building blocks for asynchronous packet routersI. M. Nedelchev, Chris R. Jesshope. 184-187 [doi]
- An efficient multiprocessor implementation scheme for real-time DSP algorithmsYu Hen Hu, Duen-Jeng Wang. 188-193 [doi]
- An energy-efficient CMOS line driver using adiabatic switchingWilliam C. Athas, Jefferey G. Koller, Lars J. Svensson. 196-199 [doi]
- Scaling of serially-connected MOSFET chainsSrinivasa Vemuru. 200-203 [doi]
- Design of a 54-bit adder using a modified Manchester carry chainReza Hashemian. 204-207 [doi]
- Low-power differential CML and ECL BiCMOS circuit techniquesK. M. Sharaf, Mohamed I. Elmasry. 208-213 [doi]
- Retiming algorithms with application to VLSI testabilityDimitrios Kagaris, Spyros Tragoudas. 216-221 [doi]
- Area, performance, and sensitizable paths [logic design]Bhanu Kapoor, V. S. S. Nair. 222-227 [doi]
- Delay independent initialization of sequential circuitsTapan J. Chakraborty, Vishwani D. Agrawal. 228-230 [doi]
- Efficient simulation of switch-level circuits in a hierarchical simulation environmentJalal A. Wehbeh, Daniel G. Saab. 231-235 [doi]
- A faster dynamic programming algorithm for exact rectilinear Steiner minimal treesJoseph L. Ganley, James P. Cohoon. 238-241 [doi]
- An improved algorithm for the generalized min-cut partitioning problemSpyros Tragoudas. 242-247 [doi]
- An ADD-based algorithm for shortest path back-tracing of large graphsR. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi. 248-251 [doi]
- Generation of color-constrained spanning trees with application in symbolic circuit analysisQicheng Yu, Carl Sechen. 252-255 [doi]