Chin-Chien Sha, R. W. Leavene. An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors. In Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994. pages 56-61, IEEE, 1994. [doi]
Abstract is missing.