Table of Contents

• Message from the General Chairs [doi]
• Program Committee [doi]
• Template Generation and Selection AlgorithmsYuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Paul M. Heysters. 2-6 [doi]
• Optimized Datapath Design by Evolutionary ComputationSérgio G. Araújo, Antônio C. Mesquita, Aloysio Pedroza. 6-9 [doi]
• A performance evaluation method for optimizing embedded applicationsMatthias Grünewald, Jörg-Christian Niemann, Ulrich Rückert. 10-15 [doi]
• A Robust Handshake for Asynchronous SystemKuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu. 16-19 [doi]
• Detailed Placement with Net Length ConstraintsBill Halpin, Naresh Sehgal, C. Y. Roger Chen. 22-27 [doi]
• Steiner Tree Construction Based on Congestion for the Global Routing ProblemLaleh Behjat, Anthony Vannelli. 28-31 [doi]
• InterconnectionModelling Using Distributed RLC ModelsDorothy Kucar, Anthony Vannelli. 32-35 [doi]
• Energy Optimization in a HW/SW Tool: Design of LowPatricia Guitton-Ouhamou, Cécile Belleudy, Michel Auguin. 38-43 [doi]
• Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache DesignKugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, Prasanna Venkatesh Kannan. 44-47 [doi]
• A Survey of Dynamic Power Optimization TechniquesLi-Chuan Weng, Xiaojun Wang, Bin Liu. 48-52 [doi]
• The Design of Low-Power Fixed-Point FIR Differentiator IP BlocksT. W. Fox, A. Carreira, L. E. Turner. 53-58 [doi]
• IP Watermarking Techniques: Survey and ComparisonAmr T. Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid. 60-65 [doi]
• The Application of 2D Algebraic Integer Encoding to a DCT IP CoreMinyi Fu, Graham A. Jullien, Vassil S. Dimitrov, Majid Ahmadi, William C. Miller. 66-69 [doi]
• Transformations of Signed-Binary Number Representations for Efficient VLSI ArithmeticBoris D. Andreev, Edward L. Titlebaum, Eby G. Friedman. 70-75 [doi]
• Digital Realization of Analogue Computing Elements Using Bit StreamsNitish Patel, George Coghill, Sing Kiong Nguang. 76-80 [doi]
• A High Performance Wide-band CMOS Transimpedance Amplifier for Optical TransceiversS. M. Rezaul Hasan. 82-85 [doi]
• A Design of CMOS Broadband Amplifier With High-Q Active InductorJhy-Neng Yang, Yi-Chang Cheng, Chen-Yi Lee. 86-89 [doi]
• A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock GenerationKuo-Hsing Cheng, Yu-lung Lo, Wen Fang Yu, Shu-Yin Hung. 90-93 [doi]
• A 5.8-GHz High Efficient, Low Power, Low Phase Noise CMOS VCO for IEEE 802.11aSau-Mou Wu, Ron-Yi Liu, Wei-Liang Chen. 94-97 [doi]
• A Low-Power Fully Differential 2.4-GHz Prescaler in 0.18µm CMOS TechnologyStephen Machan. 98-100 [doi]
• Dynamic Hardware-Software Partitioning on Reconfigurable System-on-ChipPeter Waldeck, Neil W. Bergmann. 102-105 [doi]
• Hardware Partitioning Software for Dynamically Reconfigurable SoC DesignPhilippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber. 106-111 [doi]
• A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on ChipNeil W. Bergmann, Peter Waldeck, John A. Williams. 112-115 [doi]
• Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle FiltersMagesh Sadasivam, Sangjin Hong. 116-119 [doi]
• Reconfigurable Digital Instrumentation Based on FPGACostantino Giaconia, Antonio Di Stefano, Giuseppe Capponi. 120-122 [doi]
• Introducing an FPGA based - genetic algorithms in the applications of blind signals separationH. Emam, M. A. Ashour, H. Fekry, A. M. Wahdan. 123-127 [doi]
• A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power SystemsShih-Chang Hsia. 130-133 [doi]
• Area Efficient Implementation of Noise Generation SystemDae-Ik Kim, Myung-Whan An, Ho-Yong Chung, Suk-Young Kim. 134-137 [doi]
• High-performance crossbar design for system-on-chipPanduka Wijetunga. 138-143 [doi]
• Interfacing in Microprocessor-based Systems with a Fast Physical AddressingMountassar Maamoun, Abdelhalim Benbelkacem, Daoud Berkani, Abderrezak Guessoum. 144-149 [doi]
• A Speech Speed Control Using Fourier Composite ApproachHiroto Saito, Shogo Nakamura, Masahide Yoneyama. 152-156 [doi]
• Feasibility of Fixed-Point Transversal Adaptive Filters in FPGA Devices with Embedded DSP BlocksAndrew Y. Lin, Karl S. Gugel, José Carlos Príncipe. 157-160 [doi]
• Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL ModemSergio Saponara, Luca Fanucci, L. Serafini. 161-166 [doi]
• VLSI Implementation of Very Low-Power Motion Estimator for Scaleable Coding SystemsShih-Chang Hsia. 167-170 [doi]
• A CMOS inverter TIA modeling with VHDL-AMSMohamed Karray, Patricia Desgreys, Jean-Jacques Charlot. 172-174 [doi]
• High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsimArmando Armaroli, Marcello Coppola, Mario Diaz-Nava, Luca Fanucci. 175-180 [doi]
• Java Based Co-Verification of Expedited Mobile DeviceSherif G. Aly, Ashraf M. Salem. 181-184 [doi]
• Multi-Models Adaptive Controller for Multivariable SystemsKasim A. Rashid. 185-189 [doi]
• Evaluating Template-Based Instruction Compression on Transport Triggered ArchitecturesJari Heikkinen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal. 192-195 [doi]
• RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-ChipJ. L. Silva, R. M. Costa, G. H. R. Jorge. 196-200 [doi]
• An Evolutionary Approach to Configuring an Embedded System Based on Power ConsumptionJames Northern III, Michael A. Shanblatt. 201-204 [doi]
• Pullpipelining: A technique for systolic pipelined circuitsOswaldo Cadenas, Graham M. Megson. 205-210 [doi]
• A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip DesignAli Habibi, Sofiène Tahar. 212-215 [doi]
• Design Space Exploration Methodology for High-Performance System-on-a-Chip Hardware CoresAzeddien M. Sllame. 216-221 [doi]
• Scaleable Shadow Stack for a Configurable DSP ConceptChristian Panis, Raimund Leitner, Jari Nurmi. 222-227 [doi]
• Automating Functional Coverage Analysis Based on an Executable SpecificationS. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron. 228-234 [doi]
• A System-on-a-Programmable-Chip for Real-Time Control of Massively Parallel Arrays of Biosensors and ActuatorsAldo Romani, Fabio Campi, S. Ronconi, Marco Tartagni, Gianni Medoro, Nicolò Manaresi. 236-241 [doi]
• Porosity Sensor by Using Quartz Crystals and Two Excitation SignalsVojko Matko. 242-246 [doi]
• Pipelined Sampled-Delay Focusing CMOS Implementation for Ultrasonic Digital BeamformingAbdallah Kassem, J. Wang, Abdelhakim Khouas, Mohamad Sawan, Mounir Boukadoum. 247-250 [doi]
• Designing for Test Analog Signal Processors for MEMS-Based Inertial SensorsJosé Vicente Calvano, Marcelo Lubaszewski. 251-256 [doi]
• A 0.28µm CMOS Bluetooth Frequency Synthesizer for Integration with a Bluetooth SOC Reference PlatformBogdan Georgescu, Joshua K. Nakaska, Robert G. Randall, James W. Haslett. 258-263 [doi]
• A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS TechnologyLin Jia, Alper Cabuk, Jianguo Ma, Kiat Seng Yeo. 264-269 [doi]
• Novel Design Methodology for Short-Channel MOSFET Analog CircuitsRodrigo L. Oliveira Pinto, Franco Maloberti. 270-276 [doi]
• 120nm CMOS Operational Amplifier with Pseudo-Cascodes and Positive FeedbackFranz Schlögl, Horst Zimmermann. 277-280 [doi]
• Synchronous programmable divider design for PLL Using 0.18 um cmos technologySuchitav Khadanga. 281-286 [doi]
• The Implementation of 100MHz Data Acquisition Based on FPGATao Lin, Zhou Zhengou. 287-291 [doi]
• Free-Space Optical Interconnect for High-Performance MCM SystemsChung-Seok (Andy) Seo, Abhijit Chatterjee. 294-298 [doi]
• Design Considerations for Optically Connected Systems on ChipNeal K. Bambha, Shuvra S. Bhattacharyya, Gary Euliss. 299-303 [doi]
• High-Throughput Switch-Based Interconnect for Future SoCsPartha Pratim Pande, Cristian Grecu, André Ivanov. 304-310 [doi]
• The Efficient Bus Arbitration Scheme in SoC EnvironmentChang Hee Pyoun, Chi-Ho Lin, Hi-Seok Kim, Jong-Wha Chong. 311-315 [doi]
• The Glue in a Confident SoC FlowJohn Ferguson. 316-319 [doi]
• Analysis of Coupling Noise in Dynamic CircuitMasud H. Chowdhury, Yehea I. Ismail. 320-325 [doi]
• A New Class of Computational RAM Architectures for Real-Time MPEG-4 ApplicationsMohammed Sayed, Wael M. Badawy. 328-332 [doi]
• Efficient Distributed Arithmetic Based DWT Architecture for Multimedia ApplicationsMehboob Alam, Choudhury A. Rahman, Wael M. Badawy, Graham A. Jullien. 333-336 [doi]
• The Design of a Self-Maintained Memory Module for Real-Time SystemsChia-Tien Dan Lo. 337-342 [doi]
• An Efficient Equalizer Architecture Using Tap Allocation Memory for HDTV ChannelJae-Hong Park, Jung Min Choi, Min-Ho Kim, Jong-Wha Chong. 343-349 [doi]
• Telemetry Based System for Measurement and Monitoring of Biomedical SignalsAman A. Al-Imari, Kasim A. Rashid, Mohammed Al-Dagstany. 352-356 [doi]
• Design and Implementation of a Surface Electromycogram System for Sport Field ApplicationAman A. Al-Imari, Kasim A. Rashid, Najat Hader Al-Egaidy. 357-361 [doi]
• A SoC Bio-analysis Platform for Real-time Biological Cell Analysis-on-a-ChipJ. R. Keilman, Graham A. Jullien, Karan V. I. S. Kaler. 362-368 [doi]
• An Efficient Mechanism for Debugging RTL DescriptionJiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin. 370-373 [doi]
• An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI CircuitsJiann-Chyi Rau, Kuo-Chun Kuo. 374-377 [doi]
• Symbolic Simulation as a Simplifying Strategy for SoC VerificationEmil Dumitrescu, Dominique Borrione. 378-383 [doi]
• Design, Simulation and Implementation of a Low-Power Digital Decimation Filter for G.232 StandardNikzad Babaii Rizvandi, Abdolreza Nabavi. 390-393 [doi]
• A QoS Internet Protocol Scheduler on the IXP1200 Network PlatformFernando De Bernardinis, Luca Fanucci, T. Ramacciotti, Pierangelo Terreni. 394-399 [doi]
• A Position Control System DesignRobert Gulde, Michael Weeks. 400-405 [doi]