Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model - researchr publication

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Masato Edahiro, Richard J. Lipton. Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. In 6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA. pages 143-147, IEEE Computer Society, 1996. [doi]

Abstract is missing.

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