Masato Edahiro, Richard J. Lipton. Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. In 6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA. pages 143-147, IEEE Computer Society, 1996. [doi]
@inproceedings{EdahiroL96,
title = {Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model},
author = {Masato Edahiro and Richard J. Lipton},
year = {1996},
url = {http://csdl.computer.org/comp/proceedings/glsvlsi/1996/7502/00/75020143abs.htm},
researchr = {https://researchr.org/publication/EdahiroL96},
cites = {0},
citedby = {0},
pages = {143-147},
booktitle = {6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA},
publisher = {IEEE Computer Society},
}