Table of Contents

• DARPA's Data Driven Discovery of Models (D3M) and Software Defined Hardware (SDH) ProgramsWade Shen. 1 [doi]
• Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective MiddlewareNikil Dutt. 3 [doi]
• Hardware Assurance: Trojans, Counterfeits, and Security in an Interconnected WorldMatthew J. Casto. 5 [doi]
• A Cross-Layer Perspective for Energy Efficient Processing: - From beyond-CMOS Devices to Deep LearningXiaobo Sharon Hu. 7 [doi]
• Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath DesignArman Roohi, Ramtin Zand, Ronald F. DeMara. 9-14 [doi]
• Low-Energy Deep Belief Networks Using Intrinsic Sigmoidal Spintronic-based Probabilistic NeuronsRamtin Zand, Kerem Yunus Camsari, Steven D. Pyle, Ibrahim Ahmed, Chris H. Kim, Ronald F. DeMara. 15-20 [doi]
• Maxflow: Minimizing Latency in Hybrid Stochastic-Binary SystemsPai-Shun Ting, John P. Hayes. 21-26 [doi]
• Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET Circuits and to Improve by Using Approximate CircuitsKaship Sheikh, Lan Wei. 27-32 [doi]
• Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache ArchitectureRamin Rezaeizadeh Rookerd, Somayeh Sadeghi Kohan, Zainalabedin Navabi. 33-38 [doi]
• SEPUFSoC: Using PUFs for Memory Integrity and Authentication in Multi-Processors System-on-ChipJohanna Sepúlveda, Felix Willgerodt, Michael Pehl. 39-44 [doi]
• Protecting Communication in Many-Core Systems against Active AttackersSadia Moriam, Elke Franz, Paul Walther, Akash Kumar 0001, Thorsten Strufe, Gerhard P. Fettweis. 45-50 [doi]
• A Homomorphic Encryption Scheme Based on Affine TransformsKyle Loyka, He Zhou, Sunil P. Khatri. 51-56 [doi]
• Resilient AES Against Side-Channel Attack Using All-Spin LogicQutaiba Alasad, Jiann Yuan, Jie Lin. 57-62 [doi]
• DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection NetworksMahdi Nikdast, Gabriela Nicolescu, Jelena Trajkovic, Odile Liboiron-Ladouceur. 63-68 [doi]
• A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless InterconnectsTanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Meraj Ahmed, Mark Indovina, Amlan Ganguly. 69-74 [doi]
• TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded SystemsMohamad Hammam Alsafrjalani, Tosiron Adegbija. 75-80 [doi]
• Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary AssessmentMahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi. 81-86 [doi]
• A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA ApplicationsKonstantinos Maragos, George Lentaris, Ioannis Stratakos, Dimitrios Soudris. 87-92 [doi]
• Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical ModelSneh Saurabh, Vishav Vikash. 93-98 [doi]
• Impolite High Speed Interfaces with Asynchronous Pulse LogicMerritt Miller, Carrie Segal, David Mc Carthy, Aditya Dalakoti, Prashansa Mukim, Forrest Brewer. 99-104 [doi]
• Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates InsertionWentao Dai, Peiye Liu, Weiwei Shan. 105-110 [doi]
• Energy and Performance Efficient Computation Offloading for Deep Neural Networks in a Mobile Cloud Computing EnvironmentAmir Erfan Eshratifar, Massoud Pedram. 111-116 [doi]
• Adapting Convolutional Neural Networks for Indoor Localization with Smart Mobile DevicesAyush Mittal, Saideep Tiku, Sudeep Pasricha. 117-122 [doi]
• Face Recognition with Hybrid Efficient Convolution Algorithms on FPGAsChuanhao Zhuge, Xinheng Liu, Xiaofan Zhang, Sudeep Gummadi, Jinjun Xiong, Deming Chen. 123-128 [doi]
• SCALENet: A SCalable Low power AccELerator for Real-time Embedded Deep Neural NetworksColin Shea, Adam Page, Tinoosh Mohsenin. 129-134 [doi]
• Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection MethodSuyuan Chen, Ranga Vemuri. 135-140 [doi]
• A Novel Polymorphic Gate Based Circuit Fingerprinting TechniqueTian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui. 141-146 [doi]
• Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar ArchitecturesKaveh Shamsi, Meng Li 0004, David Z. Pan, Yier Jin. 147-152 [doi]
• SRCLock: SAT-Resistant Cyclic Logic Locking for Protecting the HardwareShervin Roshanisefat, Hadi Mardani Kamali, Avesta Sasan. 153-158 [doi]
• Scalable Hardware Accelerator for Mini-Batch Gradient DescentSandeep Rasoori, Venkatesh Akella. 159-164 [doi]
• MC3A: Markov Chain Monte Carlo ManyCore AcceleratorLahir Marni, Morteza Hosseini, Tinoosh Mohsenin. 165-170 [doi]
• AEAS - Towards High Energy-efficiency Design for OpenSSL Encryption Acceleration through HW/SW Co-designChunhua Xiao, Yuhua Xie, Lei Zhang. 171-176 [doi]
• A Machine Learning Attack Resistant Dual-mode PUFQian Wang, Mingze Gao, Gang Qu. 177-182 [doi]
• A Distributed Power Grid Analysis Framework from Sequential Stream GraphChun-Xun Lin, Tsung-Wei Huang, Ting Yu, Martin D. F. Wong. 183-188 [doi]
• A Distributed Parallel Random Walk Algorithm for Large-Scale Capacitance Extraction and SimulationMingye Song, Zhezhao Xu, Wei Xue, Wenjian Yu. 189-194 [doi]
• A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing SystemsJustine Bonnot, Karol Desnos, Maxime Pelcat, Daniel Ménard. 195-200 [doi]
• Battery-aware Design Exploration of Scheduling Policies for Multi-sensor DevicesYukai Chen, Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino. 201-206 [doi]
• Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based FrameworkFanchao Wang, Hanbin Zhu, Pranjay Popli, Yao Xiao, Paul Bogdan, Shahin Nazarian. 207-212 [doi]
• Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing PathsHadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez. 213-218 [doi]
• Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMsAbhishek Das, Nur A. Touba. 219-224 [doi]
• Loss is Gain: Shortening Data for Lifetime Improvement on Low-Cost ECC Enabled Consumer-Level Flash MemoryYejia Di, Liang Shi, Congming Gao, Qiao Li, Kaijie Wu 0001, Chun Jason Xue. 225-230 [doi]
• A Novel Fault-Tolerant Last-Level Cache to Improve Reliability at Near-Threshold VoltageWei Liu, Zhigang Wei, Wei Du. 231-236 [doi]
• AB-Aware: Application Behavior Aware Management of Shared Last Level CachesSuhit Pai, Newton Singh, Virendra Singh. 237-242 [doi]
• Towards Near-Data Processing of Compare Operations in 3D-Stacked MemoryPalash Das, Hemangee K. Kapoor. 243-248 [doi]
• Utility Aware Snoozy Caches for Energy Efficient Chip Multi-ProcessorsAshwini A. Kulkarni, Shounak Chakraborty, Shrinivas P. Mahajan, Hemangee K. Kapoor. 249-254 [doi]
• SARO: A State-Aware Reliability Optimization Technique for High Density NAND Flash MemoryMyungsuk Kim, Youngsun Song, Myoungsoo Jung, Jihong Kim. 255-260 [doi]
• Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based AccelerationPeishan Tu, Chak-Wa Pui, Evangeline F. Y. Young. 261-266 [doi]
• Electromigration Design Rule aware Global and Detailed Routing AlgorithmXiaotao Jia, Jing Wang, Yici Cai, Qiang Zhou. 267-272 [doi]
• A Comparative Study of Local Net Modeling Using Machine LearningJackson Melchert, Boyu Zhang, Azadeh Davoodi. 273-278 [doi]
• Fast Timing Analysis of Non-Tree Clock Network with Shorted WiresKiwon Yoon, Daijoon Hyun, Youngsoo Shin. 279-284 [doi]
• Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing SystemsLongfei Wang, Selçuk Köse. 285-290 [doi]
• Low-Energy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and Multi-Level ClassificationSandhya Koteshwara, Keshab K. Parhi. 291-296 [doi]
• Towards A Universal Power Manager for Multi-Source Energy Scavenging and StorageSudip K. Mazumder. 297-298 [doi]
• Efficient Wireless Power Transfer for Heterogeneous Adaptive IoT SystemsInna Partin-Vaisband. 299-304 [doi]
• Low-Power Optical Interconnects based on Resonant Silicon Photonic Devices: Recent Advances and ChallengesMeisam Bahadori, Keren Bergman. 305-310 [doi]
• Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D ArchitecturesDavide Bertozzi, Marco Gavanelli, Maddalena Nonato. 311-316 [doi]
• Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-ChipSudeep Pasricha, Sai Vineel Reddy Chittamuru, Ishan G. Thakkar. 317-322 [doi]
• Silicon Photonic Interconnects: Minimizing the Controller LatencyFelipe Gohring de Magalhães, Mahdi Nikdast, Yule Xiong, Fabiano Hessel, Odile Liboiron-Ladouceur, Gabriela Nicolescu. 323-328 [doi]
• Leveraging RF Power for Intelligent Tag NetworksEmre Salman, Milutin Stanacevic, Samir Ranjan Das, Petar M. Djuric. 329-334 [doi]
• Quasi-self-powered Infrastructural Internet of Things: The Mackinac Bridge Case StudyKenji Aono, Hassene Hasni, Owen Pochettino, Nizar Lajnef, Shantanu Chakrabartty. 335-340 [doi]
• New GPR System Integration with Augmented Reality Based PositioningMauricio Pereira, Dylan Burns, Daniel Orfeo, Robert Farrel, Dryver Huston, Tian Xia. 341-346 [doi]
• MTJ Magnetization Switching Mechanisms for IoT ApplicationsAbdelrahman G. Qoutb, Eby G. Friedman. 347-352 [doi]
• Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICsCaiwen Ding, Ao Ren, Geng Yuan, Xiaolong Ma, Jiayu Li, Ning Liu, Bo Yuan 0001, Yanzhi Wang. 353-358 [doi]
• Challenges and Rewards of Implementing and Benchmarking Post-Quantum Cryptography in HardwareKris Gaj. 359-364 [doi]
• Physical Protection of Lattice-Based Cryptography: Challenges and SolutionsAyesha Khalid, Tobias Oder, Felipe Valencia, Máire O'Neill, Tim Güneysu, Francesco Regazzoni. 365-370 [doi]
• Post-Quantum Cryptography on FPGAs: The Niederreiter Cryptosystem: Extended AbstractWen Wang, Jakub Szefer, Ruben Niederhagen. 371 [doi]
• Going Small: Using the Insect Brain as a Model System for Edge Processing ApplicationsAngel Yanguas-Gil. 373-378 [doi]
• Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained DevicesGangotree Chakma, Nicholas D. Skuda, Catherine D. Schuman, James S. Plank, Mark E. Dean, Garrett S. Rose. 379-383 [doi]
• Gate-Controlled Memristors and their Applications in Neuromorphic ArchitecturesEric Herrmann, Rashmi Jha. 385-390 [doi]
• Design Exploration of IoT centric Neural Inference AcceleratorsVivek Parmar, Manan Suri. 391-396 [doi]
• Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural NetworksShaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin, Ronald F. DeMara, Deliang Fan. 397-402 [doi]
• Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep LearningYou Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner. 403-408 [doi]
• Bit-Wise Iterative Decoding of Polar Codes using Stochastic ComputingKaining Han, Junchao Wang, Warren J. Gross. 409-414 [doi]
• Comparative Study of Approximate MultipliersMahmoud Masadeh, Osman Hasan, Sofiène Tahar. 415-418 [doi]
• Dataflow-Based Mapping of Spiking Neural Networks on Neuromorphic HardwareAnup Das 0001, Akash Kumar 0001. 419-422 [doi]
• Design of Dynamic Range Approximate Logarithmic MultipliersPeipei Yin, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi. 423-426 [doi]
• Investigation and Optimization of Pin Multiplexing in High-Level SynthesisShuangnan Liu, Francis Lau, Benjamin Carrión Schäfer. 427-430 [doi]
• Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant ApplicationsHassan Afzali-Kusha, Omid Akbari, Mehdi Kamal, Massoud Pedram. 431-434 [doi]
• MuDBN: An Energy-Efficient and High-Performance Multi-FPGA Accelerator for Deep Belief NetworksYuming Cheng, Chao Wang, Yangyang Zhao, Xianglan Chen, Xuehai Zhou, Xi Li. 435-438 [doi]
• Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation ApproachMu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng. 439-442 [doi]
• BiNMAC: Binarized neural Network Manycore ACceleratorAli Jafari, Morteza Hosseini, Adwaya Kulkarni, Chintan Patel, Tinoosh Mohsenin. 443-446 [doi]
• A Hybrid Approach to Equivalent Fault Identification for Verification Environment QualificationChia-Cheng Wu, Tung-Yuan Lee, Yung-An Lai, Hsin-Pei Wang, De-Xuan Ji, Yan-Ping Chang, Teng-Chia Wang, Chin-Heng Liu, Chun-Yao Wang, Yung-Chih Chen. 447-450 [doi]
• Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D ICQi Xu, Song Chen, Bei Yu, Feng Wu. 451-454 [doi]
• Impact of Aging on Template AttacksNaghmeh Karimi, Sylvain Guilley, Jean-Luc Danger. 455-458 [doi]
• MUCH-SWIFT: A High-Throughput Multi-Core HW/SW Co-design K-means Clustering ArchitectureHadi Mardani Kamali, Avesta Sasan. 459-462 [doi]
• An Efficient Cache Management Scheme for Capacitor Equipped Solid State DrivesCongming Gao, Liang Shi, Yejia Di, Qiao Li, Chun Jason Xue, Edwin Hsing-Mean Sha. 463-466 [doi]
• Evaluation of the Complexity of Automated Trace Alignment using Novel Power Obfuscation MethodsBozhi Liu, Kemeng Chen, Minjun Seo, Janet Meiling Wang, Roman Lysecky. 467-470 [doi]
• th-Order Delta-Sigma Modulator with One Reconfigurable AmplifierJae-hyeon Sung, Kwang Sub Yoon. 471-474 [doi]
• On the Design of Reliable Heterogeneous Systems via Checkpoint Placement and Core AssignmentEdwin Hsing-Mean Sha, Hailiang Dong, Weiwen Jiang, Qingfeng Zhuge, Xianzhang Chen, Lei Yang 0018. 475-478 [doi]
• SAT-Lancer: A Hardware SAT-Solver for Self-VerificationBuse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler. 479-482 [doi]
• FLexiTASK: A Flexible FPGA Overlay for Efficient MultitaskingJoel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, Christophe Bobda. 483-486 [doi]
• An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power GatingSumanta Pyne. 487-490 [doi]
• Optimal Topology-Aware PV Panel Floorplanning with Hybrid OrientationSara Vinco, Enrico Macii, Massimo Poncino. 491-494 [doi]
• ADDHard: Arrhythmia Detection with Digital Hardware by Learning ECG SignalSai Manoj Pudukotai Dinakarrao, Axel Jantsch. 495-498 [doi]
• Hardening AES Hardware Implementations Against Fault and Error Inject AttacksLake Bu, Michel A. Kinsy. 499-502 [doi]
• SimTRaX: Simulation Infrastructure for Exploring Thousands of CoresKonstantin Shkurko, Tim Grant, Erik Brunvand, Daniel Kopta, Josef B. Spjut, Elena Vasiou, Ian Mallett, Cem Yuksel. 503-506 [doi]
• Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC DesignsAliyar Attaran, Tyler David Sheaves, Praveen Kumar Mugula, Hamid Mahmoodi. 507-510 [doi]
• Innovating at Cloud Speed for IoT, AI, and Semiconductor DesignDavid B. Pellerin. 511 [doi]
• Mixed-Signal POp/J Computing with Nonvolatile MemoriesMohammad Reza Mahmoodi, Dmitri B. Strukov. 513 [doi]
• Low Power and Trusted Machine LearningAvesta Sasan, Qi Zu, Yanzhi Wang, Jae-sun Seo, Tinoosh Mohsenin. 515 [doi]
• Securing the Systems of the Future - Techniques for a Shifting Attack SpaceIoannis Savidis, Swarup Bhunia, Gang Qu, Matthew J. Casto, Jeremy Muldavin. 517 [doi]