A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range - researchr publication

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Hyuk-Jun Sung, Kwang Sub Yoon. A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 553-556, IEEE, 1999. [doi]

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