Table of Contents

• A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management SystemsChih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang. 1-4 [doi]
• Adaptive frequency-controlled ultra-fast hysteretic buck converter for portable devicesKwang Ho Kim, Bai-Sun Kong, Young-Hyun Jun. 5-8 [doi]
• Design of high dimming ratio power-LED driver with preloading inductor current methodologyKeon Lee, Dong-Hun Lee, Su-hun Yang, Ji-hyun Park, Kwang Sub Yoon. 9-12 [doi]
• NP dynamic CMOS resurrection with carbon nanotube field effect transistorsYanan Sun, Volkan Kursun. 13-16 [doi]
• A novel charge recovery logic structure with complementary pass-transistor networkJingyang Li, Yimeng Zhang, Tsutomu Yoshihara. 17-20 [doi]
• Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemesYunLong Zhang, Qiang Tong, Li Li, Wei Wang, Ken Choi, JongEun Jang, Hyobin Jung, Si-Young Ahn. 21-24 [doi]
• Multi-core architecture for video decodingJae-Jin Lee, Kyungjin Byun, Nak-Woong Eum. 25-28 [doi]
• Real-time stereo matching for 3D hand gesture recognitionPo-Kuan Huang, Tung-Yang Lin, Hsu-Ting Lin, Chi-Hao Wu, Ching-Chun Hsiao, Chao-Kang Liao, Peter Lemmens. 29-32 [doi]
• An inter-frame macroblock schedule for memory access reduction in H.264/AVC bi-directional predictionChae-Eun Rhee, Hyun Kim, Hyuk-Jae Lee. 33-36 [doi]
• A fast Multi-scale Retinex algorithm using dominant SSR in weights selectionChan Young Jang, Jae Hwan Lim, Young-Hwan Kim. 37-40 [doi]
• Brightness preserving contrast enhancement using polynomial histogram amendmentPramila Welling, Sung Hoon Kim, Sang-Bock Cho. 41-44 [doi]
• Design of high-speed support vector machine circuit for driver assistance systemSoojin Kim, Seonyoung Lee, Kyeongsoon Cho. 45-48 [doi]
• Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interfaceWoo-Rham Bae, Byoung-Joo Yoo, Deog Kyoon Jeong. 49-52 [doi]
• A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technologyTaeho Kim, Deog Kyoon Jeong. 53-56 [doi]
• A highly integrated IR-UWB transceiver for communication and localizationOleksiy Klymenko, Denys I. Martynenko, Gunter Fischer. 57-60 [doi]
• A TDC-based skew compensation technique for high-speed output driverDebashis Dhar, Inhwa Jung, Chulwoo Kim. 61-64 [doi]
• 60-GHz voltage-controlled oscillator and frequency divider in 0.25-µm SiGe BiCMOS technologyJeong Min Lee, Woo-Young Choi, Holger Rücker. 65-67 [doi]
• A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolatorYoung-Ho Choi, Jae-Yoon Sim, Hong June Park. 68-71 [doi]
• Contention and energy aware mapping for real-time applications on Network-on-ChipBingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao. 72-76 [doi]
• Target voltage independent capacitance measurement circuit implemented by 0.18 µm CMOS for PWM-MEMS controlKazutoshi Kodama, Makoto Ikeda. 77-80 [doi]
• A WDR method with low noise in digital circuitYounghwan Yun, Myoungsun Kim. 81-83 [doi]
• Redundant-dictionary based adaptive sampling for transient ECG signal measurementZhongyun Yuan, Jun Dong Cho. 84-87 [doi]
• Current equalization scheme for parallel low-dropout regulatorsSiddharth Katare, Narayanan Natarajan. 88-91 [doi]
• A CMOS voltage reference combining body effect with switched-current techniqueNing Ren, Hao Zhang, Tsutomu Yoshihara. 92-95 [doi]
• Design and analysis of a power-efficient cascode-compensated amplifierShafqat Ali, Steve Tanner, Pierre-André Farine. 96-99 [doi]
• Spur suppression in frequency synthesizer using switched capacitor arrayDebashis Mandal, Pradip Mandal, Tarun Kanti Bhattacharyya. 100-103 [doi]
• A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technologyJinsoo Rhim, Kwang-Chun Choi, Woo-Young Choi. 104-107 [doi]
• A digitally enhanced low-distortion delta-sigma modulator for wideband applicationJae-Hyeon Shin, Kang-Il Cho, Gil-Cho Ahn. 108-111 [doi]
• Digitizing the feedback signal in a magnetic field (AMR) sensor system using delta sigma modulator topologyTommy Halim, Karsten Leitis. 112-115 [doi]
• A DLL-based FSK demodulator for 5.8GHz DSRC/ETC RF receiverHung-Wen Lin, Hsin-Lin Hu, Wu-Wei Lin. 116-119 [doi]
• Signal-dependent analog-to-digital converter based on MINIMAX samplingIgors Homjakovs, Masanori Hashimoto, Takao Onoye, Tetsuya Hirose. 120-123 [doi]
• A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applicationsSang-Pil Nam, Yongmin Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee. 124-127 [doi]
• A programmable delay-locked loop based clock multiplierSungken Lee, Geontae Park, Hyungtak Kim, Jongsun Kim. 128-130 [doi]
• A wide dynamic range CMOS image sensor based on a new gamma correction techniqueYeonseong Hwang, Jangwoo Lee, Daeyun Kim, Minkyu Song. 131-134 [doi]
• Energy-efficient high-level synthesis for HDR architectures with clock gatingHiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa. 135-138 [doi]
• Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processorsMitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui. 139-142 [doi]
• Die matching algorithm for enhancing parametric yield of 3D ICsSangdo Park, Taewhan Kim. 143-146 [doi]
• Thermal-aware body bias modulation for high performance mobile coreChungki Oh, Hyung-Ock Kim, Jun Seomun, Wook Kim, Jaehan Jeon, Kyung Tae Do, Hyo-Sig Won, Kee Sup Kim. 147-150 [doi]
• A synthesis algorithm for customized heterogeneous multi-processorsRahim Soleymanpour, Siamak Mohammadi, Hamed Rajabi. 151-154 [doi]
• Dynamically changeable secure scan architecture against scan-based side channel attackYuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa. 155-158 [doi]
• A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problemDongwoo Lee, Junwhan Ahn, Kiyoung Choi. 159-162 [doi]
• Performance aware partitioning for 3D-SOCsAmit Kumar 0004, Sudhakar M. Reddy, Bernd Becker 0001, Irith Pomeranz. 163-166 [doi]
• Hybrid Mesh-Ring wireless Network on Chip for multi-core systemMohamed A. Abd El ghany, Mohamed A. Wanas, Mohamed Zaki. 167-170 [doi]
• Design of H.264 video encoder with C to RTL design toolSangchul Kim, Hyunjin Kim, Taeil Chung, Jin-Gyeong Kim. 171-174 [doi]
• Practical and efficient SOC verification flow by reusing IP testcase and testbenchZhaohui Hu, Arnaud Pierres, Shiqing Hu, Chen Fang, Philippe Royannez, Eng Pek See, Yean Ling Hoon. 175-178 [doi]
• Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedureShao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong. 179-184 [doi]
• Integration of dual channel timing formatter system for high speed memory test equipmentJaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang. 185-187 [doi]
• Error Injection & Correction: An efficient formal logic restructuring algorithmChing-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang. 188-191 [doi]
• An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuitsIl-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong June Park. 192-195 [doi]
• Design of logic-compatible embedded DRAM using gain memory cellWeijie Cheng, Jeong-Wook Cho, Yeonbae Chung. 196-199 [doi]
• NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cellsZhao Chuan Lee, Kim Ming Ho, Zhi-Hui Kong, Tony T. Kim. 200-203 [doi]
• Task mapping techniques for embedded many-core SoCsJunya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, Koji Inoue. 204-207 [doi]
• Dynamic load balancing algorithm for system on chipShinwon Lee, V. Meka, Mingu Jeon, Nagoo Sung, Jeongnam Youn. 208-211 [doi]
• A study of mobile Optical Image Stabilization system for mobile cameraSeung-Kwon Lee, In-Ho Kook, Jin-Hyeung Kong. 212-214 [doi]
• 7.7Gbps encoder design for IEEE 802.11n/ac QC-LDPC codesYongmin Jung, Chulho Chung, Jaeseok Kim, Yunho Jung. 215-218 [doi]
• Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processorByung-Jun Choi, Jae Do Lee, Myung Hoon Sunwoo, Xinmiao Zhang. 219-222 [doi]
• Low-latency area-efficient decoding architecture for shortened reed-solomon codesHoyoung Yoo, Youngjoo Lee, In-Cheol Park. 223-226 [doi]
• Design of low-power high-radix switch fabric with partially-activated input and output linesJihyun Ryoo, Seuk Son, Jaeha Kim. 227-230 [doi]
• Efficient IFFT architecture design for OFDM applicationsIn-Gul Jang, Dae Ho Kim, Ho-Yun Yi, Jin-Gyun Chung, Kyung-Ju Cho. 231-234 [doi]
• Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer schemeYoshichika Fujioka, Michitaka Kameyama. 235-238 [doi]
• Parallel and digit-serial implementations of area-efficient 3-Operand Decimal AddersTso-Bing Juang, Hsin-Hao Peng, Han-Lung Kuo. 239-242 [doi]
• Performance hotspot based CUDA accelerationFahian Ahmed, Byeong Kil Lee, Bum Joo Shin, Duk Soo Son, Young Choon Woo, Wan Choi. 243-246 [doi]
• Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAMByung-Min Lee, Gi-Ho Park. 247-250 [doi]
• Si-based D-band frequency conversion circuitsDong-hyun Kim, Jongwon Yun, Jae-Sung Rieh. 251-253 [doi]
• Terahertz image sensors using CMOS Schottky barrier diodesRuonan Han, Yaming Zhang, Youngwan Kim, Dae-Yeon Kim, Hisashi Shichijo, K. O. Kenneth. 254-257 [doi]
• Development of millimeter-wave CMOS power amplifiers at National Taiwan UniversityKun-You Lin, Tian-Wei Huang, Huei Wang. 258-261 [doi]
• InP HBT voltage controlled oscillator for 300-GHz-band wireless communicationsJae-Young Kim, Ho-Jin Song, Katsuhiro Ajito, Makoto Yaita, Naoya Kukutsu. 262-265 [doi]
• SiGe BiCMOS technology for mm-wave systemsHolger Rücker, Bernd Heinemann. 266-268 [doi]
• Transmitter antennas for wireless capsule endoscopyEng Gee Lim, Zhao Wang, Fang Zhou Yu, Tammam Tillo, Ka Lok Man, Jing Chen Wang, Meng Zhang. 269-272 [doi]
• A loosely-coupled binding model for Wireless Sensor NetworksDanny Hughes 0001, Ka Lok Man, Zhun Shen, Kyung Ki Kim. 273-276 [doi]
• An efficient history-based routing algorithm for interconnection networksSanaz Rahimi Moosavi, Chia-Yuan Chang, Amir-Mohammad Rahmani, Juha Plosila, Ka Lok Man, Taikyeong T. Jeong, Eng Gee Lim. 277-280 [doi]
• Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communicationAmir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Ka Lok Man, Youngmin Kim, Hannu Tenhunen. 281-284 [doi]
• Assuring system reliability in wireless sensor networks via verification and validationZhun Shen, Ka Lok Man, Chi-Un Lei, Eng Gee Lim, Joongho Choi. 285-288 [doi]
• A multi-core mapping implementation of 3780-point FFTEnle Chen, Yun Chen, Yizhi Wang, Chen Chen 0011, Xiaoyang Zeng. 289-292 [doi]
• Application-specific Instruction-Set Processor design methodology for wireless image transmission systemsTsuyoshi Isshiki, Hao Xiao, Hsuanchun Liao, Dongju Li, Hiroaki Kunieda. 293-296 [doi]
• Design and implementation of a video display processing SoC for full HD LCD TVHongbin Sun, Longjun Liu, Qiubo Chen, Baolu Zhai, Nanning Zheng. 297-300 [doi]
• A smart platform with cognitive techniques for narrowband power line communicationYan Zhao, Qingqing Yang, Xiaofang Zhou, Nianrong Zhou, Yufeng Cui. 301-304 [doi]
• A low cost soft mapper for turbo equalization with high order modulationLicai Fang, Qinghua Guo, Defeng Huang, Sven Nordholm. 305-308 [doi]
• Perspectives on 3D ToF sensor SoC integration for user interface applicationTae-Yon Lee, Jung-Kyu Jung, Dong-Ki Min, Yoondong Park, Kwanghyuk Bae, Tae-Chan Kim. 309-312 [doi]
• Face detection based on chrominance and luminance for simple designYoungjin Kim, Sungkwang Cho, Byungjoon Back, Taechan Kim. 313-316 [doi]
• Sensitivity improvement in FSI CIS using the M1ToP™ smart process techniqueManlyun Ha, Sun Choi, DongHun Cho, Hosoo Kim, Jungyeon Cho, Youngsun Oh, Jongman Kim, Sangwon Yoon, Changhoon Choi, Juneseok Lee, Juil Lee, Joon Hwang. 317-319 [doi]
• Pixel design and photodiode process technology for image sensor applicationsMinkyu Kang, Hoon Jang, Sunjae Hwang, Soeun Park, Sanghwa Kim, Hosoon Ko, Changhun Han, Joon Hwang. 320-323 [doi]
• Pedestrian detection and tracking using deformable part models and Kalman filteringShubham Mittal, Twisha Prasad, Suraj Saurabh, Xue Fan, Hyunchul Shin. 324-327 [doi]
• Improved nonlocal means denoising for images with tone gradientsAlexander Getman, Se-Hwan Yun, Tae-Chan Kim. 328-331 [doi]
• A low-cost architecture for multi-mode Reed-Solomon decoderYun Chen, Yuebin Huang, Wei Meng, Zhiyi Yu, Xiaoyang Zeng. 332-334 [doi]
• High-throughput turbo decoder design with new interconnection network for LTE/LTE-A systemJen-Yu Hou, Tsao-Shuan Lee, Pei-Yun Tsai. 335-338 [doi]
• Efficient EMS decoding for non-binary LDPC codesLeixin Zhou, Jin Sha, Zhongfeng Wang. 339-342 [doi]
• A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A systemChi-Hsuan Hsieh, Ming-Yong Lee, Yuan-Hao Huang. 343-346 [doi]
• A study into high-throughput decoder architectures for high-rate LDPC codesYeong-Luh Ueng, Chung-Chao Cheng. 347-350 [doi]
• Circuit design for carbon nanotube field effect transistorsHaiqing Nan, Wei Wang, Ken Choi. 351-354 [doi]
• Refinement of depth maps generated by low-cost depth sensorsKrishna Rao Vijayanagar, Maziar Loghman, Joohee Kim. 355-358 [doi]
• An efficient dual-supply design for low-power mobile systemsHoi-Jin Lee, Youngmin Shin, Jae Cheol Son, Tae-Hee Han, Bai-Sun Kong. 359-362 [doi]
• Real-time digital image stabilization using motion sensors for search range reductionJun-Hoe Heo, Jong-Hak Kim, Dong-Hun Lee, Yong-Han Kim, Jun Dong Cho. 363-366 [doi]
• High energy efficient ultra-low voltage SRAM design: Device, circuit, and architectureTony T. Kim, Bo Wang 0020, Anh-Tuan Do. 367-370 [doi]
• A novel analog-to-residue converter for biomedical DSP applicationDi Zhu 0003, Qi Huang, Zhao Chuan Lee, Yuanjin Zheng, Liter Siek. 371-374 [doi]
• CMOS-MEMS capacitive sensors for intra-cranial pressure monitoring: Sensor fabrication & system designArup K. George, Wai Pan Chan, Margarita Sofia Narducci, Zhi-Hui Kong, Minkyu Je. 375-378 [doi]
• An optimum RF link for implantable devices with rectification of transmission errorsZhong-Qiang Ding, Kiat Seng Yeo. 379-382 [doi]
• A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductorHaitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu. 383-386 [doi]
• Low power implantable neural recording front-endAnh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo. 387-390 [doi]
• Millions to thousands issues through knowledge based SoC CDC verificationYoungchan Lee, Namdo Kim, Jay B. Kim, Byeong Min. 391-394 [doi]
• Verification of massive advanced node SoCsDaeseo Cha, HyunWoo Koh, NamPhil Jo, Jay B. Kim, Byeong Min, Karthik Kothandapani, Riccardo Oddone, Adam D. Sherer. 395-397 [doi]
• A web service for automated IP/SoC verification using computers on networkYeon-Ho Im, Seong-Hee Yim, Jay B. Kim. 398-401 [doi]
• System-level simulation acceleration for architectural performance analysis using hybrid virtual platform systemKyuho Shim, Woojoo Kim, Kwang-Hyun Cho, Byeong Min. 402-404 [doi]
• How to automate millions lines of top-level UVM testbench and handle huge register classesNamdo Kim, Young-Nam Yun, Young-Rae Cho, Jay B. Kim, Byeong Min. 405-407 [doi]
• A leakage reduced HVIC with coarse-fine UVLOSung-Pah Lee, Kunhee Cho, Minwoo Lee, Wookang Jin. 408-411 [doi]
• Low-offset comparator using capacitive self-calibrationLei Sun, Kong-Pang Pun. 412-414 [doi]
• Design of LED driver using digital up/down counterJae-Hyoun Park, Hyung-Do Yoon. 415-418 [doi]
• A high-speed adaptive linear equalizer with ISI level detection using periodic training patternJin-Cheol Seo, Tae-Ho Kim, Taek-Joon An, Kwan Yoon, Jin-Ku Kang. 419-422 [doi]
• A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOSSeung-Wook Oh, Hyung-Min Park, Joon-Hyup Seo, Jae-Young Jang, Gi-Yeol Bae, Jin-Ku Kang. 423-426 [doi]
• A background calibration method for DAC mismatch correction in multibit sigma-delta modulatorsShafqat Ali, Steve Tanner, Pierre-André Farine. 427-430 [doi]
• Time-domain temperature sensor using two stage vernier type time to digital converter for mobile applicationMinsoo Kang, Jinwook Burm. 431-434 [doi]
• A design and integration of Parametric Measurement Unit on to a 600MHz DCLEdward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim. 435-438 [doi]
• A low power CMOS receiver front-end for long term evolution systemsKuang-Hao Lin, Tai-Hsuan Yang, Jan-Dong Tseng. 439-442 [doi]
• A low-complexity bio-medical signal receiver for wireless body area networkChih-Hung Lin, Robert Chen-Hao Chang, Tz-Han Pang, Kuang-Hao Lin. 443-446 [doi]
• Multi-function unit for LED lightingSehoon Yoo, Sehyun Song, Kichul Kim, Chanwoo Park, Jungchul Gong. 447-450 [doi]
• An ultra high-speed time-multiplexing Reed-Solomon-based FEC architectureJeong-In Park, Jewong Yeon, Seung-Jun Yang, Hanho Lee. 451-454 [doi]
• An 880 / 1760 MHz tunable bandwidth active RC low-pass filter using high gain amplifierSanghoon Park, Kwang-Ho Ahn, Ki-Jin Kim. 455-457 [doi]
• A 28nm 6T SRAM memory compiler with a variation tolerant replica circuitSharad Gupta, Parvinder Kumar Rana. 458-461 [doi]
• Verification of an efficient Match-line Sense Amplifier for the High Frequency Search OperationGun Sang Park, Hyun-Jin Choi, Nagakarthik Tumuganti, Jun Rim Choi. 462-465 [doi]
• Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuitsHailong Jiao, Volkan Kursun. 466-469 [doi]
• Proposal of a new ultra low leakage 10T sub threshold SRAM bitcellAnis Feki, Bruno Allard, David Turgis, Jean-Christophe Lafont, Lorenzo Ciampolini. 470-474 [doi]
• Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFSWoojin Yun, Jongpil Jung, Kyungsu Kang, Chong-Min Kyung. 475-478 [doi]
• Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAMJunha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-Ook Jung. 479-482 [doi]
• High efficiency multi-channel LED driver based on SIMO switch-mode converterLuchen Yu, Yuan Zhu, Minjie Chen, T. Yoshihara. 483-486 [doi]
• Low power consumption for detecting current zero of synchronous DC-DC buck converterXuan-Dien Do, Seok-Kyun Han, Sang-Gug Lee. 487-490 [doi]
• An efficient JPEG decoding and scaling method for digital TV platformsTaeyoung Lee, Cheul-Hee Hahm, Gunyoung Bae, Byunghoan Chon, Kangwook Chun. 491-493 [doi]
• Design of multi-core rasterizer for parallel processingJung-Yong Lee, Hoon Heo, Kwang-Yeob Lee, Yong-Seo Koo. 494-497 [doi]
• Low-complexity frame scheduler using shared frame memory for multi-view video codingMinsu Choi, Jinsang Kim, Ik Joon Chang, Won-Kyung Cho. 498-502 [doi]
• Development of a verification platform for intelligent surveillance camera systemsSu-Hyun Lee, Yong-jin Jeong. 503-505 [doi]
• Traffic sign detection and identification using SURF algorithm and GPGPUDajun Ding, Jihwan Yoon, Chanho Lee. 506-508 [doi]
• FPGA implementation of stereoscopic image proceesing architecture base on the gray-scale projectionHi-Seok Kim, Sea-Ho Kim, Won-Ki Go, Sang-Bock Cho. 509-512 [doi]
• One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating techniqueYoung Kyun Park, Ji-Hoon Lim, Jae-Kyung Wee, Inchae Song. 513-516 [doi]