Tso-Bing Juang - researchr alias

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Viewing Publication 1 - 27 from 27

2024

Design of Automatic Generators for Fibonacci Q- matrix based Encryption/Decryption CircuitsTso-Bing Juang, Huang-Sen Chiu. isocc 2024: 199-200 [doi]

2023

Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS)Tso-Bing Juang, Chun-Chi Fan, Guan-Zhong Lin. isocc 2023: 185-186 [doi]

2019

Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number SystemsTso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin. isocc 2019: 180-181 [doi]

2018

Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number SystemsTso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin. isocc 2018: 170-171 [doi]

2017

Low-area implementations of concurrent error detection logarithmic processorsTso-Bing Juang, Ying-Ren Lee. isocc 2017: 131-132 [doi]

2016

Low-cost concurrent error detection schemes for logarithmic convertersTso-Bing Juang, Ying-Ren Lee, Chin-Chieh Chiu. isocc 2016: 213-214 [doi]

Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its ApplicationsTso-Bing Juang, Ying-Ren Lee. isvlsi 2016: 625-630 [doi]

2014

Fast binary to BCD converters for decimal communications using new recoding circuitsTso-Bing Juang, Yu-Ming Chiu. isicir 2014: 188-191 [doi]

2012

2011

Area-efficient 3-input decimal adders using simplified carry and sum vectorsTso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo. vlsi 2011: 25-30 [doi]

2010

n + 1 Adder Design With Simple Correction SchemesTso-Bing Juang, Chin-Chieh Chiu, Ming-Yu Tsai. tcas, 57-II(3):198-202, 2010. [doi]

Area-efficient parallel-prefix Ling addersTso-Bing Juang, Pramod Kumar Meher, Chung-Chun Kuan. apccas 2010: 736-739 [doi]

2009

n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu. tcas, 56-II(3):260-261, 2009. [doi]

A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing ApplicationsTso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng. tcas, 56-II(12):931-935, 2009. [doi]

50 Years of CORDIC: Algorithms, Architectures, and ApplicationsPramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna. tcas, 56-I(9):1893-1907, 2009. [doi]

2008

A novel VLSI iterative divider architecture for fast quotient generationTso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li. iscas 2008: 3358-3361 [doi]

Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator ImplementationsTso-Bing Juang. tcas, 55-II(11):1139-1143, 2008. [doi]

2006

Area/Delay Efficient Recoding Methods for Parallel CORDIC RotationsTso-Bing Juang. apccas 2006: 1539-1542 [doi]

2005

Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property DesignShen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee. tcas, 52-I(8):1568-1579, 2005. [doi]

Low-error carry-free fixed-width multipliers with low-cost compensation circuitsTso-Bing Juang, Shen-Fu Hsiao. tcas, 52-II(6):299-303, 2005. [doi]

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final AdditionTso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan. ieicet, 88-D(7):1464-1471, 2005. [doi]

2004

A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotationsShen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang. spl, 11(2):152-155, 2004. [doi]

Para-CORDIC: parallel CORDIC rotation algorithmTso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai. tcas, 51-I(8):1515-1524, 2004. [doi]

2002

Partition methodology for the final adder in a tree-structure parallel multiplier generatorTso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao. apccas 2002: 471-474 [doi]

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