Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li. A novel VLSI iterative divider architecture for fast quotient generation. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 3358-3361, IEEE, 2008. [doi]
Abstract is missing.