A novel VLSI iterative divider architecture for fast quotient generation - researchr publication authors

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Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li. A novel VLSI iterative divider architecture for fast quotient generation. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 3358-3361, IEEE, 2008. [doi]

This author has not been identified. Look up 'Tso-Bing Juang' in GoogleThis author has not been identified. Look up 'Sheng-Hung Chen' in GoogleThis author has not been identified. Look up 'Shin-Mao Li' in Google

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