Abstract is missing.
- Self-Supervised Contrastive Representation Learning for Time-Series ClassificationKunpeng Li, Jong Chul Lee. 1-2 [doi]
- LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight CryptographyNgoc Hung Nguyen, Duc Hong An Le, Vu Trung Duong Le, Van Tinh Nguyen, Tuan Hai Vu, Hoai Luan Pham, Yasuhiko Nakashima. 1-2 [doi]
- High Voltage Driver with Multiple Outputs Capable of Independent PWM ControlJae-Hyoun Park. 1-2 [doi]
- A High-Efficiency High-Data-Rate Wireless Power and Data Transfer IC Using Orthogonal Codes for Miniatureized Multi-Channel Neural Interface SystemsChan Park, Sohmyung Ha, Minkyu Je. 1-3 [doi]
- An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA BiochipsKensuke Fukui, Shigeru Yamashita. 1-2 [doi]
- Design of a Multilingual Translation System with Personalized Voice CharacteristicsChen-Hua Chen, Guan-Yu Lai, Chuan Lee, Chang-yu Wu, Kuan-Lin Liu, Shin-Chi Lai. 1-2 [doi]
- Self-sustainable Triple-input Triple-output Power Management Unit for Battery-less IoT Application with Low-power Time-monitoring MPPTYen-Yun Huang, Po-Hung Chen. 3-4 [doi]
- Comparative Analysis of Quantum Adder Circuits in Computation Accuracy on Noisy Quantum ComputersSungyoun Hwang, Hyoju Seo, Yongtae Kim. 5-6 [doi]
- Interface Circuits for Piezoelectric Polyvinylidene Fluoride (PVDF) FilmsCarl Lester Fabian, Marc D. Rosales, John Richard E. Hizon. 5-6 [doi]
- A Cap-less LDO Regulator with Improved Load Regulation using Adaptive Feedback Control and Modified Voltage DamperTzung-Je Lee, Han Yi Chiu. 9-10 [doi]
- An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS ProcessPradyumna Vellanki, Hung-Che Tseng, Ying-Xuan Chen, L. S. S. Pavan Kumar Chodisetti, Chua-Chin Wang. 11-12 [doi]
- Optimal Efficiency True Random Number Generator with Discrete-time Chaos for Low-Cost ApplicationsTzung-Je Lee, Cheng-Han Wu. 15-16 [doi]
- A High-Gain Transimpedance Amplifier Using Highly-Linear and Symmetric Multi-Stage Pseudo-ResistorsSoheila Khakneshin, Mehdi Saberi, Alexandre Schmid. 19-20 [doi]
- Compact Inductor-less CMOS PAM4 VCSEL Driver for High-speed Optical CommunicationsJunsei Oshika, Shogo Ishida, Daisuke Ito, Makoto Nakamura. 21-22 [doi]
- A Low-power PLL with a Standby ModeYu-Chun Hsiao, Rui-Cheng Ai, Zhen-Jie Hong, Yu-lung Lo, Jen-Chieh Liu. 23-24 [doi]
- A Fast-Lock All-Digital PLL with a TDC-based FLLChanghoon Chae, Jongsun Kim. 25-26 [doi]
- A 339-nW 32.768-kHz DFLL-Based Reference Clock Generator with an Embedded Temperature SensorShuan Yang, Tai-Hong Chen, Yu-Chi Wang, Chia-Hsi Fang, Chun-Yu Lin, Shan-Chih Tsou, Shon-Hang Wen, Kuan-Dar Chen, Tsung-Hsien Lin. 27-28 [doi]
- A Programmable DLL-based Delay ChainYu-Wei Huang, Cheng-En Wu, Wei-Bin Yang, Jen-Chieh Liu. 29-30 [doi]
- A 12.8-Gb/s/lane, 1.03-pJ/b Transmitter With Reconfigurable Charge-Injecting Crosstalk Cancellation For Capacitively Coupled High-Density InterconnectsYoochang Kim, Seunghoon Yi, Seung Chae Jung, Hee-Cheol Joo, Sung Chul Lee, Young Ha Hwang. 31-32 [doi]
- A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link SetupYufeng Ge, Zheng Jiang, Yibin Fu, Yaolong Zhang, Jingbo Wang, Hong Zhang. 33-34 [doi]
- A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial LinksJaewon Lee, Seoyoung Jang, Donggeon Kim, Yujin Choi, Sungyu Song, Gain Kim. 35-36 [doi]
- A Reference Voltage Generator Using Level Tracking Scheme for Low-Swing PAM-3 SignalingSeul-Ki Han, Won Young Lee. 37-38 [doi]
- A 2.5-12.3 Gb/s continuous-rate referenceless CDR with counter-based unlimited frequency detectionYujin Na, Jin-Ku Kang. 39-40 [doi]
- Clock Recovery Circuit for 3-Gsymbol/s/lane MIPI C-PHY ReceiverDong-Seob Shin, Jong Ho Park, Changmin Song, Seong-Yun Kim, Hyeonseok Lee, Jinyeong Lee, Young-Chan Jang. 45-46 [doi]
- A High-Speed HBM Receiver Design for High-Performance Computing SystemsThinh Nguyen-Viet, Gyung-Su Byun. 47-48 [doi]
- 3-Gsymbol/s/lane MIPI C-PHY Receiver with Feed-forward Level-dependent EqualizationJong Ho Park, Minjun Cho, Juncheol Kim, Haewoon Son, Hyeon-Ho Kim, Young-Chan Jang. 49-50 [doi]
- A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD ProcessSoumika Majumder, Lean Karlo Santos Tolentino, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Chua-Chin Wang. 51-52 [doi]
- A LoRaWAN Enabled Sensor-Based System for Detecting Rodent ActivitySzu-Ting Wang, Shang-Sian Wu, Kuo-Cheng Tseng, Li-Chuan Hsu, Song-Min Ke, Shin-Chi Lai. 53-54 [doi]
- Performance Evaluation of a RISC-V CPU at Cryogenic Temperature for Future Quantum ControlY. S. Chong, V. P. Nambiar, A. Mani, V. Leong, C. P. Y. Wong, A. T. Do. 67-68 [doi]
- An 800-MS/s 10b Pipelined ADC with Floating Ring AmplifiersChao-Yen Hsu, Mu-Heng Pi, Tai-Cheng Lee. 69-70 [doi]
- Power Reduction Techniques for Energy-Efficient Audio Continuous-Time Delta-Sigma ModulatorWonseon Lee, Youngcheol Chae. 71-72 [doi]
- An Integrator Time-Constant Calibration Scheme with Modified Voltage to Digital ConverterTing-Yu Syu, Yin-Qin Ye, Hsin-Liang Chen, Hsiao-Hsing Chou, Jen-Shiun Chiang. 73-74 [doi]
- A Robust DT ∆Σ Modulator for High-Resolution Sensor Against Temperature VariationsJihun Choi, Sangwook Na, Taehun Kim, Jeongjin Roh. 75-76 [doi]
- An Energy Efficient Period-modulation-based Current-to-digital Converter for FET-type SensorsWonseok Heo, Hoyong Seong, Donghyun Youn, Minkyu Je, Sohmyung Ha. 77-78 [doi]
- A 14-GHz-Band Low-Supply-Voltage Low-Phase-Noise LC-VCO IC with Harmonic Tuned LC Tank in 45-nm CMOS SOIChenxu Zhao, Mengchu Fang, Toshihiko Yoshimasu. 79-80 [doi]
- 5GHz Automatic Amplitude Calibration VCO Using Synchronous Clock Temperature CompensationChia-Chia Wang, Yue-Fang Kuo. 81-82 [doi]
- A 38-GHz Stacked-FET Linear Power Amplifier with Novel Phase Linearizer Circuit in 45-nm CMOS SOIZhewen Wei, Toshihiko Yoshimasu. 85-86 [doi]
- 5G Millimeter-Wave RF Front-End Module ICs Design in Silicon CMOS SOI vs. GaNDonald Y. C. Lie, L.-W. Ouyang, Clint Sweeney, Jill C. Mayeda, J. Lopez. 87-88 [doi]
- A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing ApplicationsVishnu P. Nambiar, Y. S. Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, T. Mitra, A. T. Do. 89-90 [doi]
- Lookup Table and Neural Network Based Decoders for Real Time Quantum Error CorrectionY. S. Chong, U. Jana, S. Y. Soh, V. P. Nambiar, W. L. Goh, B. Wang, A. T. Do. 91-92 [doi]
- CGLA: Coarse-Grained Linear Array for Multi-Hash Acceleration in Blockchain MiningPham Hoai Luan, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima. 93-94 [doi]
- UCP: A Unified Cryptographic Processor for High Performance and Low Power Security ApplicationsVu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran, Thi Diem Tran, Yasuhiko Nakashima. 95-96 [doi]
- Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level SynthesisHyeri Roh, Woo-seok Choi. 97-98 [doi]
- MHC : Multi-flit HBM Crossbar with Enhancing Performance and Resource UtilizationJaehun Jung, Jin Hyeong Park, Young-Gil Jeong, Jeongwoo Park. 99-100 [doi]
- LEAP: LLW RowHammer Mitigation SystemYooJin Kim, Yesin Ryu, Jungrae Kim. 101-102 [doi]
- High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security ApplicationsDuc Hong An Le, Vu Trung Duong Le, Viet Anh Ho, Van Tinh Nguyen, Hoai Luan Pham, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima. 103-104 [doi]
- A Simple Up-and-Down Weight Update Method for Tiny 8-bit Quantized CNN TrainingChanyung Kim, Eunchong Lee, KyungHo Kim, Sung-Joon Jang, Sang-Seol Lee. 109-110 [doi]
- Hybrid CC-LSTM Algorithm for SOC Estimation and Its Dual-Mode Hardware DesignYiwen Peng, Gexuan Wu, Lei Huang, Bing Li. 113-114 [doi]
- On Exploring Non-negative Matrix Factorization for Deep Neural Network CompressionMahendra Kumar Gurve, Gaurav Kumar, Sankar Behera, Yamuna Prasad, Satyadev Ahlawat. 115-116 [doi]
- A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-ComputingSunjoo Whang, Soyeon Um, Sangwoo Ha, Hoi-Jun Yoo. 117-118 [doi]
- 2Edward Jongyoon Choi, Jiho Chun, Byeongseon Choi, Sohmyung Ha, Ik Joon Chang, Minkyu Je. 119-120 [doi]
- Quantum Battery Optimization through Quantum Machine Learning TechniquesVu Tuan Hai, Vo Minh Kiet, Vu Trung Duong Le, Pham Hoai Luan, Le Bin Ho, Yasuhiko Nakashima. 121-122 [doi]
- Efficient Cardiovascular Disease Diagnosis System for an Wearable Device based on Multi Stage BCResNetJungbeom Ko, JaeYun Park, Minjeong Kim, Soomi Jeong, Hyunchul Kim, Jungsuk Kim. 123-124 [doi]
- An Effective Neural Network Model Protection Method Against Model Stealing Attacks for Image Classification ApplicationsLih-Yih Chiou, Yu-Hung Lee, Chung-Chieh Chiu, Shun-Hsiu Hsu. 125-126 [doi]
- Fast and Accurate Curvilinear OPC with ML-Guided Curve CorrectionSeohyun Kim, Gangmin Cho, Shilong Zhang, Youngsoo Shin. 127-128 [doi]
- CARDS: A Novel Detailed Macro Placement Framework for Minimizing WirelengthYen-Lin Chua, Meng-Shan Wu, Yu-Guang Chen. 131-132 [doi]
- IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing OptimizationYu-Guang Chen, Hung-Han Chang, Yu-Chuan Liang, Wen-Hsiang Chang, I-Ching Tsai, Chih-Wei Lin, Yun-Chih Chang, Mango Chia-Tso Chao. 133-134 [doi]
- Optimizing and Addressing Stitch Challenges in High-NA EUV Lithography for Large Die DesignsYongchan James Ban, Gangsic Kim, Hosoon Shin. 135-136 [doi]
- An Invariant Interconnect Delay Monitoring Circuit for 3D System ScalingSeung-Mo Noh, Kee-Won Kwon. 137-138 [doi]
- Enabling cell selection optimization for non-traditional CMOS topologiesAndré Lucas Chinazzo, Norbert Wehn, Sani R. Nassif. 139-140 [doi]
- AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNsJiho Lee, Jieui Kang, Eunjin Lee, Yejin Lee, Jaehyeong Sim. 143-144 [doi]
- An Embedded core of Content-based maskable CAM exploring Longest Prefix Match fashionAtsushi Ooka, Kazunari Inoue, Takaya Miyazawa. 145-146 [doi]
- D-band Low Noise Amplifier with Improved Linearity in 90-nm BiCMOS9HP ProcessSeunjae Shin, Yeongmin Jang, Jinho Jeong. 149-150 [doi]
- Write Bias Scheme Optimization of Ferroelectric Field-Effect-Transistor (FeFET) Synapse for Accurate On-chip TrainingSeungmin Kang, Sangwan Kim, Sihyun Kim. 153-154 [doi]
- Leveraging Algorithm-based Fault Tolerance for Propagation Error Detection in NPUsSihyung Kim, Seokin Hong. 157-158 [doi]
- Automorphism Architecture for Bootstrapping Homomorphic EncryptionHanyoung Lee, Hanho Lee. 159-160 [doi]
- Design of an Area-Efficient and Error-Reduced CMOS Approximate AdderNovi Prihatiningrum, Jungu Kang, Chanyeong Choi, Yeongkyo Seo. 161-162 [doi]
- A 12-28 Gb/s Temperature Compensated PAM-4 Transmitter with 7B4Q Maximum Transition Avoidance and Fractional-Spaced FFESua Kim, Jin-Ku Kang. 163-164 [doi]
- Enhanced Image Classification through Layer-Wise Feature Concatenation in Deep Neural NetworksAkshay Kumar Sharma, Kyung Ki Kim. 165-166 [doi]
- Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation SpeedJiwon Lee, Hyeonjun Cheon, Ho Sung Lee, Ik-Hyeon Jeon, Joo-Hyung Chae. 167-169 [doi]
- A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access ModesHyeonjun Cheon, Ho Sung Lee, Jiwon Lee, Ik-Hyeon Jeon, Joo-Hyung Chae. 169-170 [doi]
- Hardware-aware Network Compression for Hybrid Vision Transformer via Low-Rank ApproximationBeom-Jin Kang, Nam-Joon Kim, Hyun Kim 0001. 171-172 [doi]
- A Low-Noise Capacitively-Coupled Chopper Instrumentation Amplifier with SAR-Assisted Low Current Ripple Reduction TechniqueJungkook Jo, Jaehoon Jun. 173-174 [doi]
- Implementation of Activation Functions using various approximation methodsJiho Park, Geon Shin, Hoyoung Yoo. 175-176 [doi]
- A 2T1C eDRAM-based Compute-In-Memory Macro with 8-to-l Column Multiplexing Scheme for Highly Sparse Binarized Deep Neural NetworksShin-Uk Kang, Seung-Mo Jin, Min-Gwon Song, Dong-hyun Lee, Woo-Suk Jung, Min-Seong Choo. 177-178 [doi]
- An Energy-Efficient Hardware Accelerator for On-Device Inference of YOLOXKyungmi Kim, Soeun Choi, Eunkyeol Hong, Yoonseo Jang, Jaehyeong Sim. 179-180 [doi]
- FB-SKP: Front-Back Structured Kernel Pruning via Group Convolution without Increasing MemoryKwanghyun Koo, Hyun Kim. 181-182 [doi]
- AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS TechnologyJin-Won Hyun, Dana Kim, Kyung-Sik Choi, Jae-Won Nam. 183-184 [doi]
- Accelerating Embedded WebAssembly Based on FPGAJinyeol Kim, Raehyeong Kim, Jongwon Oh, Seung Eun Lee. 187-188 [doi]
- Si-Backside Side-Channel Leakage Measurement and SimulationRikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Akhilesh Kumar, Norman Chang. 189-190 [doi]
- SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstrationAtsushi Hasegawa, Makoto Ikeda, Ichiro Naka, Kunio Uchiyama. 191-192 [doi]
- Opportunities and Challenges of DRAM-based Computing-in-Memory for AI AcceleratorSangjin Kim, Hoi-Jun Yoo. 193-194 [doi]
- Botnet Classification using Machine LearningMan Ni, Gabriela Mogos. 197-198 [doi]
- Design of Automatic Generators for Fibonacci Q- matrix based Encryption/Decryption CircuitsTso-Bing Juang, Huang-Sen Chiu. 199-200 [doi]
- State of Charge Estimation for Lithium-Ion Batteries Based on Informer-LSTM Hybrid NetworkNingfei Song, Nanlin Jin, Jingchen Wang, Jie Zhang 0030, Ka Lok Man, Jeremy S. Smith, Yutao Yue. 201-202 [doi]
- Designs of Dual-band Metamaterials for Near-field Wireless Power TransmissionXiaozhe Ji, Jingchen Wang, Ka Lok Man, Eng Gee Lim, Yutao Yue, Jiafeng Zhou. 203-204 [doi]
- DDS-PLL Architecture for Adaptive Beam SteeringGianfranco Avitabile, Ka Lok Man, Claudio Talarico. 205-206 [doi]
- Low-Cost Dual-Band Active Transponder for SAR Satellites CalibrationGianfranco Avitabile, Marco Rossano, Ka Lok Man. 207-208 [doi]
- A small and low power ergodic sequential logic neuron model for neural prosthesesSota Ohtaki, Hiroyuki Torikai. 209-210 [doi]
- Effect of Mutual Information on Chaotic Attractor Classification Accuracy Using Neural NetworkMasaki Fujita, Yoko Uwate, Yoshifumi Nishio. 209-210 [doi]
- Design of Resonant Converter with Genetic- Algorithm OptimizationRintaro Kaneiso, Ayano Komanaka, Yinchen Xie, Yutaro Komiyama, Akihiro Konishi, Kien Nguyen 0002, Hiroo Sekiya. 211-212 [doi]
- Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel RoutingMasayuki Shimoda, Atsushi Takahashi 0001. 213-214 [doi]
- Study on Reservoir Computing Combining Chaotic Circuits and Periodic OscillatorsIhara Ayase, Yoko Uwate, Yoshifumi Nishio. 215-216 [doi]
- Waveform Classification by Two-Layer Reservoir Computing with van der Pol OscillatorsYasufumi Kajino, Yoko Uwate, Yoshifumi Nishio. 217-218 [doi]
- Enhancing Embedded Super-Resolution Accelerators: Techniques for Hardware Performance ImprovementZhicheng Hu, Liang Chang 0002. 222-223 [doi]
- Real-Time Ultrasound Imaging System for Drone and Robotic ApplicationsJinhong Ahn, Silin Chen, Junwei Feng, Hyunseung Lee 0001, Junbeom Park, Hyoungjoon Kim, Jerald Yoo. 224-225 [doi]
- Effect of Coupling Strength on Synchronization Phenomena in Chaotic Circuits with Unidirectional CouplingKohei Suzue, Yoko Uwate, Yoshifumi Nishio. 226-227 [doi]
- Analysis of the synchronization performance of wireless functional electronic stimulation central pattern generatorRikuto Nozu, Hiroyuki Torikai. 228-229 [doi]
- Implementation of Wireless Spiking Neural Network for Classifications on MNIST DatasetHaruto Ota, Jiaying Lin, Ryuji Nagazawa, Kien Nguyen 0002, Hiroo Sekiya, Won-Joo Hwang. 230-231 [doi]
- Switching Phenomena by Adding a Memristor to a Chaos CircuitTaishi Segawa, Yoko Uwate, Yoshifumi Nishio. 232-233 [doi]
- Synchronization Phenomena in Coupled van der Pol Oscillators with Memristor Couplings as Ladder StructureYukinojo Kotani, Yoko Uwate, Yoshifumi Nishio. 234-235 [doi]
- Wafer-level Packaging Platform for MEMS Sensor ApplicationsTaehyun Kim, Junmo Yang, Chungmo Yang, Sung-Hoon Choa, Hee Yeoun Kim. 238-239 [doi]
- Smartphone-based Road Condition Sensing using Machine Learning techniquesLuepol Pipanmekaporn, Suwatchai Kamonsantiroj, Ruslee Sutthaweekul, Wilaiporn Lee, Kanabadee Srisomboon. 246-247 [doi]
- Rank Reversal Avoiding Algorithm for Modern Cooperative Spectrum SensingWilaiporn Lee, Kanabadee Srisomboon. 248-249 [doi]
- Machine Learning for Indoor Localization using CSI TechniqueWilaiporn Lee, Cattareeya Suwanasri, Luepol Pipanmekaporn, Kanabadee Srisomboon. 250-251 [doi]
- Enhancing Event Extraction and Impact Analysis with Knowledge Graph Augmented TransformerKallaya Songklang, Kanabadee Srisomboon, Wilaiporn Lee, Akara Prayote. 252-253 [doi]
- A New Service Time Framework for Expressway Toll Lane Capacity ModelPattarapon Klaykul, Akara Prayote, Wilaiporn Lee. 254-255 [doi]
- Automatic Speech Recognition Techniques for Transcription of Thai Traditional Medicine TextsJettasic Popun, Wilaiporn Lee, Akara Prayote. 256-257 [doi]
- Unseen Named Entity Recognition for Thai LanguageWatcharet Kuntichod, Wilaiporn Lee, Akara Prayote. 258-259 [doi]
- Enhancing Multi-parent Selection Algorithm Exploiting MPTCP ProtocolAdisorn Kheaksong, Wilaiporn Lee, Kanabadee Srisomboon. 260-261 [doi]
- A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping MechanismJiann-Chyi Rau, Wei-Bin Yang, Yu-lung Lo, Chin-Yuan Shih, Cheng-Kai Lin, Che-Chia Chuang. 262-263 [doi]
- A bandgap reference with low TC of 1.363ppm/°C across wide temperature range for PMICsMinho Seo, Hongil Yoon. 264-265 [doi]
- An All-Digital Standard-Cell-Based Resistive-Sensing Display Panel/Chip Crack DetectorHyunwook Lee, Hee-Cheol Joo, Seung Chae Jung, Seunghoon Yi, Young Ha Hwang. 268-269 [doi]
- Power-efficiency estimation of exponential horn driver circuit for low-power optical linkDaisuke Ito, Masataka Furuta, Yasuhiro Takahashi, Makoto Nakamura. 274-275 [doi]
- Phase Locked Loop with Ramp Generator for FMCW LiDAR TX in 28-nm CMOSDohyun Shin, Jonghyun Kim, Jinwook Burm. 276-277 [doi]
- A DLL-Based Three-Step Time-to-Digital Converter for Time-of-Flight ApplicationsXinye Gu, Mingyi Chen. 278-277 [doi]
- A Resilient All-Digital PLL Using Ping-Pong Delay LineHsiang-Kai Teng, Shi-Yu Huang. 280-281 [doi]
- Low-Power Frequency-Mode Temperature Sensing Circuit with Subthreshold Operational AmplifierTzung-Je Lee, Po-Hsuan Hsiao. 284-285 [doi]
- Reconfigurable Gaussian filtering TSP readout circuit for Flexible AMOLED DisplayJuwon Ham, Wooseok Jang, Hamin Lee, Sangweun Kim, Dabin Yun, JunSeong Kim, Seunghoon Ko. 288-289 [doi]
- Signal Shifting-based Reusable Redundant TSV Structure for Infrastructure TSVDonghyun Han, Sunghoon Kim, Sungho Kang 0001. 290-291 [doi]
- 3T1R Memristor Crossbar Architecture for Diverse Logic ImplementationIkkyum Kim, Heechun Park. 292-293 [doi]
- An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node LevelsSuzuki Koki, Shigeru Yamashita. 294-295 [doi]
- Calibrating the Dark Count Rate of Single Photon Avalanche Diodes Using Linear RegressionYoungmin Cho, Jinwook Burm. 296-297 [doi]
- Design of a Low-Cost Stochastic Computing-based Median Filter for Digital Image ProcessingDonghui Lee, Yongtae Kim. 298-299 [doi]
- 22/16nm High Speed and Area Efficient Automotive Grade STT-MRAM Memory Compiler for 2~128MbS. Kumar, V. Kumar, A. Antonyan, B. Prickett, U. K. Bobbili, D. Chakraborty, D. Nguyen, S. Sharma, H. Harshul, A. Dang. 302-303 [doi]
- A 28-nm 10.4-fJ/b Cryogenic embedded DRAM with 3T1C Gain Cell and MBIST at 4-KelvinJiapei Zheng, Xinkai Nie, Zhenghang Zhi, Zhidong Tang, Qi Liu 0010, Xufeng Kou, Chixiao Chen. 306-307 [doi]
- Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security ApplicationsNhat Nguyen Dinh, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Yasuhiko Nakashima. 308-309 [doi]
- A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-ChipBinh Kieu-Do-Nguyen, Khai-Duy Nguyen, Nguyen The Binh, Tuan-Kiet Dang, Duc-Hung Le, Cuong Pham-Quoc, Ngoc Thinh Tran, Cong-Kha Pham, Trong-Thuc Hoang. 310-311 [doi]
- Effective Data-Width Aware ECC Scheme for HBMSeung-Ho Shin, Youngki Moon, Byungsoo Kim, Sungho Kang 0001. 316-317 [doi]
- Cost-Efficient Partially-Parallel LDPC Decoder Architecture for 50G-PON StandardJeongwon Choe, Youngjoo Lee. 318-319 [doi]
- Evaluating the Impact of In-band ECC on GPU PerformanceSoyoung Park, Jungrae Kim. 320-321 [doi]
- Improved Contrast Enhancement Algorithm for Night Vision Systems using Thermal CameraCheol Ho Choi, Jeongwoo Cha, Joonhwan Han, HyunMin Choi, Jungho Shin. 322-323 [doi]
- FPGA Design of a Masked AES Circuit with PPRM-based S-BoxYuhui Liu, Taosong Zhao, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 328-329 [doi]
- Enhancing Efficiency in Computational Intensive Domains via Redundant Residue Number SystemsSoudabeh Mousavi, Dara Rahmati, Saeid Gorgin 0001, Jeong-A Lee. 330-331 [doi]
- Design of a 3D-IC based AI-Vision SoCSangmuk Lee, Jongseung Lee, Jeong-Ho Woo, Jinhong Park. 332-333 [doi]
- Analysis and Design of CRC-based SENT Interface for Future Automotive ApplicationsEsha Muzammal, Saransh Rajjarwal, Min-Chae Kim, Gyung-Su Byun. 334-335 [doi]
- An Approximate Multiplier Design Based on Mitchell's AlgorithmXiangyu Li, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama. 336-337 [doi]
- 3 Architecture with Low Area Overhead: Accelerator Support ModuleFriedrich Pauls, Sebastian Haas, Yogesh Verma. 340-341 [doi]
- PEMAC: A Posit EM AC with LDD and Logarithm ApproximationHojin Sung, Yeonjoo Nam, Woong Choi. 342-343 [doi]
- On-Device Eye Tracking System with Dual Lightweight AI ProcessorJongwon Oh, Raehyeong Kim, Jinyeol Kim, Seung Eun Lee. 344-345 [doi]
- The hardware implementation of QARMA-64 with RoCC on FPGA for memory encryptionHyunjae Park, Jin-Ku Kang, Yongwoo Kim. 346-347 [doi]
- System-on-Chip iot for Smart Poultry ManufacturingWai Yie Leong, Yuan Zhi Leong, Wai San Leong. 348-349 [doi]
- Efficient Hardware Implementation of Nonlinear Activation Function For Inference ModelSnehit Chunarkar, Samba Raju Chiluveru. 350-351 [doi]
- A Novel Area Efficient Approximate Stochastic Computing Approach for Edge DevicesKeerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi. 352-353 [doi]
- A Fully 4-bit Quantized MobileNet-SSDAeri Kim, Yumi Kim, Eunchong Lee, Minkyu Lee, Sang-Seol Lee. 354-355 [doi]
- BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning AccelerationEunseo Kim, Subean Lee, Chaeyun Kim, HaYoung Lim, Jimin Nam, Jaehyeong Sim. 356-357 [doi]
- Resource-efficient DL Model Inference with Weight Clustering and Zero-skippingAbhishek Yadav, Masahiro Fujita, Binod Kumar 0001. 358-359 [doi]
- Fast Performance and Power Profiler for SRAM Compute-in-Memory-based AcceleratorsLih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Tzung-Jin Tsai. 360-361 [doi]
- Simplified Real-time Categorized Vehicle Counting and Speed EstimationIan Christian Fernandez, Percival Magpantay, Marc D. Rosales, John Richard E. Hizon. 362-363 [doi]
- Error-Resilient Binary Neural Network Inference with Selective Recompute-Based Error CorrectionGil-Ho Kwak, Tae-Hwan Kim. 364-365 [doi]
- Integrating Noise Classification and Speech Enhancement Model for Hearing AidsYing-Hsiu Hung, Yen-Ching Chang, Shin-Chi Lai, Wen-Ho Juang, Ming-Hwa Sheu, Jeng-Dao Lee. 368-369 [doi]
- Integrating CNN and RCE Networks for Efficient On-Device Image ClassificationKyou-Jung Son, Seokhun Jeon, Byung-Soo Kim. 370-371 [doi]
- A Hybrid Precision Network with Efficient Processing Elements for 3D Hand Pose EstimationJaehyeon So, Jong Hwan Ko. 372-373 [doi]
- Strategic Improvements in CNN Accelerators: Optimizing PE Utilization for MobileNetV2Eunchong Lee, Sang-Seol Lee, Minkyu Lee, KyungHo Kim, Sung-Joon Jang. 374-375 [doi]
- Autoencoder-based Knowledge Distillation For Quantized YOLO DetectorYugwon Seo, Jin-Ku Kang, Yongwoo Kim. 376-377 [doi]
- Row-Efficient Pruning for In-Memory Convolutional Weight MappingJohnny Rhe, Jong Hwan Ko. 378-379 [doi]
- An Im2col Architecture Using The Benes Network For Deep Learning Hardware AcceleratorsSanghyun Kim, KyungHo Kim, Yumi Kim, Aeri Kim, Sung-Joon Jang. 380-381 [doi]
- C-AFA: A Conditionally Approximate Full Adder for Efficient DNN Inference in CIM ArraysJuhong Park, Jong Hwan Ko. 382-383 [doi]
- Lightweight DL-based Drone Image Classification for Surveillance ApplicationsAbhishek Yadav, Masahiro Fujita, Binod Kumar 0001. 386-387 [doi]
- Tailoring Backbone Architectures for SSDAmrita Rana, Kyung Ki Kim. 388-389 [doi]
- Differential Injection-Locked Frequency Tripler with a Low-coupling 8-shaped TransformerMao-Hsiu Hsu, Sheng-Lyang Jang, Meng-Ting Lin, Wen Cheng Lai, Miin-Horng Juang. 388-389 [doi]
- LogicEdu: Enhancing Computational Logic Understanding through Web-Based Boolean Logic Simplification ToolLongfan Li, Chao Wang, Wangzilu Lu, Yuhang Zhang 0008, Leilai Shao, Yanan Sun, Jian Zhao 0004, Yongfu Li 0002. 390-391 [doi]
- Scan Architecture with Data Observation for Multiple Scan Cell Fault DiagnosisJuyong Lee, Sooryeong Lee, Hayoung Lee, Sungho Kang 0001. 392-393 [doi]
- A 60 GHz CMOS OOK Receiver with 7.7 GHz Bandwidth for Wireless Proximity CommunicationSijin Jang, Gunwoo Jeong, HwaYoung Jeong, Hyunchol Shin. 392-393 [doi]
- INC: In channel Crossing ECC for LPDDR Compression Attached Memory ModuleYoonyul Yoo, Jungrae Kim. 394-395 [doi]
- APAPG: Address Pre-Processed ALPG for High-Speed Linear TestSooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang 0001. 396-397 [doi]
- Low-cost SDR-based Reader for Chipless Sensor TagT. Sukapan, P. Tambanjong, R. Sutthaweekul, Pisit Vanichchanunt, Sukritta Paripurana, W. Saelee, A. Marindra. 396-397 [doi]
- Detecting and assignment of unexpected tasks in SoC design process using genetic programmingAdam Górski, Maciej Ogorzalek. 398-399 [doi]
- Timing Analysis with Analytical SensitivityJan Lappas, Norbert Wehn, Sani R. Nassif. 400-401 [doi]
- Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level EffectsYoonjae Lee, Heechun Park. 402-403 [doi]
- Optimized Instruction Set Architecture for Programmable Memory Test Pattern GenerationSeokmin Park, Jewoo Park, Young-Woo Lee. 404-405 [doi]
- Optimized Multiplier Architecture: Integrating Det/Pre-Encoder and Compound GateDaseul Moon, Jisoo Lee, Woong Choi. 406-407 [doi]
- Production-Oriented Design for High Parallel Test EfficiencyJaehwan Shin, Young-Woo Lee. 410-411 [doi]
- High Quality Power-Aware Verification of Mixed Signal designs using UPF checkersGokul T, Ajay B. S, Raveendranathreddy P. 422-423 [doi]
- Device Parameter Extraction Method for Training Performance Predicting ModelsMinjeong Kim, Taehoon Kim, Woo-seok Choi. 424-425 [doi]
- Analysis of Test Environment Configuration for High-Speed Link Chip MeasurementYunseong Jo, Hyuntae Kim, Jaeduk Han. 430-431 [doi]
- A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial LinksSeoyoung Jang, Jaewon Lee, Yujin Choi, Donggeon Kim, Gain Kim. 432-433 [doi]