A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology - researchr publication

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Jinsoo Rhim, Kwang-Chun Choi, Woo-Young Choi. A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology. In International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012. pages 104-107, IEEE, 2012. [doi]

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