A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit

Sharad Gupta, Parvinder Kumar Rana. A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit. In International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012. pages 458-461, IEEE, 2012. [doi]

Abstract

Abstract is missing.